[PATCH][SH] info registers

[Andrew STUBBS]

Hi,

sh-tdep.c contains quite a lot of code to implement the 'info registers' 
command (and friends).

It has a number of issues:
  - The double and vector registers are only in hex.
  - Invalid registers are still printed for some types (not that GDB 
knows which registers are invalid - that's my next patch).
  - The double registers are incorrectly named dr0..dr7, and the vector 
registers incorrectly named fv0..fv3. They should be dr0,dr2,dr4... and 
fv0,fv4,...

I have discovered that the default code (when the architecture may 
override) does everything the SH code does right and yet does not do 
everything it does wrong. Specifically all the above problems are 
addressed.

I therefore propose removing all this garbage entirely.

Before

   (gdb) info all-registers
   r0             0x0      0
   r1             0x0      0
   r2             0x0      0
   r3             0x0      0
   r4             0x0      0
   r5             0x0      0
   r6             0x0      0
   r7             0x0      0
   r8             0x0      0
   r9             0x0      0
   r10            0x0      0
   r11            0x0      0
   r12            0x0      0
   r13            0x0      0
   r14            0x0      0
   r15            0x0      0
   pc             0x0      0
   pr             0x0      0
   gbr            0x0      0
   vbr            0x0      0
   mach           0x0      0
   macl           0x0      0
   sr             0x0      0
   fpul           0                (raw 0x00000000)
   fpscr          0x0      0
   fr0            0                (raw 0x00000000)
   fr1            0                (raw 0x00000000)
   fr2            0                (raw 0x00000000)
   fr3            0                (raw 0x00000000)
   fr4            0                (raw 0x00000000)
   fr5            0                (raw 0x00000000)
   fr6            0                (raw 0x00000000)
   fr7            0                (raw 0x00000000)
   fr8            0                (raw 0x00000000)
   fr9            0                (raw 0x00000000)
   fr10           0                (raw 0x00000000)
   fr11           0                (raw 0x00000000)
   fr12           0                (raw 0x00000000)
   fr13           0                (raw 0x00000000)
   fr14           0                (raw 0x00000000)
   fr15           0                (raw 0x00000000)
   ssr            0x0      0
   spc            0x0      0
   r0b0           0x0      0
   r1b0           0x0      0
   r2b0           0x0      0
   r3b0           0x0      0
   r4b0           0x0      0
   r5b0           0x0      0
   r6b0           0x0      0
   r7b0           0x0      0
   r0b1           0x0      0
   r1b1           0x0      0
   r2b1           0x0      0
   r3b1           0x0      0
   r4b1           0x0      0
   r5b1           0x0      0
   r6b1           0x0      0
   r7b1           0x0      0
   bank           0
   dr0     0x0000000000000000
   dr1     0x0000000000000000
   dr2     0x0000000000000000
   dr3     0x0000000000000000
   dr4     0x0000000000000000
   dr5     0x0000000000000000
   dr6     0x0000000000000000
   dr7     0x0000000000000000
   fv0     0x00000000      0x00000000      0x00000000      0x00000000
   fv1     0x00000000      0x00000000      0x00000000      0x00000000
   fv2     0x00000000      0x00000000      0x00000000      0x00000000
   fv3     0x00000000      0x00000000      0x00000000      0x00000000

After

   (gdb) info all-registers
   r0             0x0      0
   r1             0x0      0
   r2             0x0      0
   r3             0x0      0
   r4             0x0      0
   r5             0x0      0
   r6             0x0      0
   r7             0x0      0
   r8             0x0      0
   r9             0x0      0
   r10            0x0      0
   r11            0x0      0
   r12            0x0      0
   r13            0x0      0
   r14            0x0      0
   r15            0x0      0
   pc             0x0      0
   pr             0x0      0
   gbr            0x0      0
   vbr            0x0      0
   mach           0x0      0
   macl           0x0      0
   sr             0x0      0
   fpul           0 (raw 0x00000000)
   fpscr          0x0      0
   fr0            0 (raw 0x00000000)
   fr1            0 (raw 0x00000000)
   fr2            0 (raw 0x00000000)
   fr3            0 (raw 0x00000000)
   fr4            0 (raw 0x00000000)
   fr5            0 (raw 0x00000000)
   fr6            0 (raw 0x00000000)
   fr7            0 (raw 0x00000000)
   fr8            0 (raw 0x00000000)
   fr9            0 (raw 0x00000000)
   fr10           0 (raw 0x00000000)
   fr11           0 (raw 0x00000000)
   fr12           0 (raw 0x00000000)
   fr13           0 (raw 0x00000000)
   fr14           0 (raw 0x00000000)
   fr15           0 (raw 0x00000000)
   ssr            0x0      0
   spc            0x0      0
   r0b0           0x0      0
   r1b0           0x0      0
   r2b0           0x0      0
   r3b0           0x0      0
   r4b0           0x0      0
   r5b0           0x0      0
   r6b0           0x0      0
   r7b0           0x0      0
   r0b1           0x0      0
   r1b1           0x0      0
   r2b1           0x0      0
   r3b1           0x0      0
   r4b1           0x0      0
   r5b1           0x0      0
   r6b1           0x0      0
   r7b1           0x0      0
   dr0            0 (raw 0x0000000000000000)
   dr2            0 (raw 0x0000000000000000)
   dr4            0 (raw 0x0000000000000000)
   dr6            0 (raw 0x0000000000000000)
   dr8            0 (raw 0x0000000000000000)
   dr10           0 (raw 0x0000000000000000)
   dr12           0 (raw 0x0000000000000000)
   dr14           0 (raw 0x0000000000000000)
   fv0            {0x0, 0x0, 0x0, 0x0}     {0, 0, 0, 0}
   fv4            {0x0, 0x0, 0x0, 0x0}     {0, 0, 0, 0}
   fv8            {0x0, 0x0, 0x0, 0x0}     {0, 0, 0, 0}
   fv12           {0x0, 0x0, 0x0, 0x0}     {0, 0, 0, 0}

Thanks

Andrew Stubbs
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