introduce SH 2a simulator

[Andrew Cagney]

Can you revise the ChangeLogs as follows:

> Index: include/gdb/ChangeLog
> from  Alexandre Oliva  <aoliva@redhat.com>
> 
> 	2004-02-13  Michael Snyder  <msnyder@redhat.com>
> 	* sim-sh.h: Add new sh2a banked registers.

Write this as

YYYY-MM-DD  Michael Snyder ....

	Committed by ....
	* change.

Rewrite the below as:

YYYY-MM-DD  Michael Snyder ....

	Committed by ...
	* final set of changes

instead of a long winded change history.

and repost.

Andrew



> Index: sim/sh/ChangeLog
> from  Alexandre Oliva  <aoliva@redhat.com>
> 
> 	Introduce SH2a support.
> 	2004-02-13  Michael Snyder  <msnyder@redhat.com>
> 	* interp.c (sim_fetch_register, sim_store_register): 
> 	Revert overloading of tbr and ibnr onto ssr and spc.
> 	Implement proper handling of tbr and bank registers.
> 	2004-02-12  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c, interp.c: Revert the splitting of the jump table
> 	into two pieces.  Instead, change it from char to short.
> 	2004-02-11  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement ldbank, stbank, and resbank.
> 	* interp.c (saved_state): Add ibnr and ibcr.  Move bfd_mach
> 	to end of struct.  Add regstack pointer.
> 	(IBNR, IBCR, BANKN, ME, SET_BANKN, SET_ME): New macros.
> 	(init_dsp): Allocate space for 512 register banks.
> 	(sim_store_register, sim_fetch_register): For now, overload
> 	tbr and ibnr onto ssr and spc.
> 	(trap): For now, use trap #13 and trap #14 to set ibnr and ibcr.
> 	2004-02-05  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement rtv/n, mulr, divs, and divu.
> 	2004-01-30  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement clips, clipu.
> 	* interp.c (union saved_state_type): Add BO, CS.
> 	2004-01-29  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement movmu, movml.
> 	(gensim_caselist): Add tokens for r15 and multiple regs.
> 	2004-01-27  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement nott, movrt, movu, 
> 	long versions of mov.  Add mov.l @-<REG_N>,R0.
> 	(gensim_caselist): Add defaults to switch statements.
> 	* interp.c (do_long_move_insn): New function.
> 	2004-01-21  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement movi20 and movi20s.
> 	Implement mov.b and mov.w with disp12.
> 	2004-01-20  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement mov.l with 12-bit displacement.
> 	2004-01-16  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement fmov.[sd] with 12-bit displacement.
> 	* gencode.c (op tab): Implement bset/bclr.
> 	2004-01-15  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (op tab): Implement bit manipulation insns.
> 	Implement jsr/n.  Turn on implementations of remaining
> 	16-bit sh2a insns.
> 	* interp.c (do_blog_insn): Implement binary logic insns.
> 	2004-01-14  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c (conflict_warn, warn_conflicts): Temporary debugging.
> 	2004-01-13  Michael Snyder  <msnyder@redhat.com>
> 	* gencode.c: Move movx/movy insns into separate switch 
> 	statement (thereby freeing space in the 8-bit opcode table).
> 	(filltable): Make index auto instead of static.
> 	(gensim_caselist): Generate default case here instead of in caller.
> 	(gensim): Generate two separate switch statements.  Call
> 	gensim_caselist once for each (for movsxy_tab and for tab).
> 	* interp.c (init_dsp): Don't swap contents of sh_dsp_table 
> 	any more.  Instead use it directly in its own switch statement.
> 	2004-01-09  Michael Snyder  <msnyder@redhat.com>
> 	* interp.c (sim_load): Save the bfd machine code.
> 	(sim_create_inferior): Ditto.
> 	* gencode.c (op tab): If machine == sh2a, reject instructions
> 	that are disabled on that chip.
> 	* interp.c (union saved_state_type): Add tbr register.
> 	* gencode.c (op tab): Add some new sh2a insns.
>