[RFA] New "audio" instructions for fujitsu frv sim
Michael Snyder
msnyder@redhat.com
Wed Oct 1 20:48:00 GMT 2003
Michael Snyder wrote:
> Hi Dave,
>
> Here's the implementation for the fr405 "audio" instructions,
> complete with testsuite.
>
> Cheers,
> Michael
Oops, and I should have added,
opcodes/ChangeLog:
* frv-desc.c: Regenerate.
* frv-opc.c: Regenerate.
* frv-opc.h: Regenerate.
* frv-desc.h: Regenerate.
sim/frv/ChangeLog:
* decode.c, decode.h, sem.c, model.c, cpu.c, cpu.h,
arch.c, arch.h, cpuall.h: Regenerate.
>
>
> ------------------------------------------------------------------------
>
> src/cpu/ChangeLog:
> 2003-10-01 Michael Snyder <msnyder@redhat.com>
>
> * frv.cpu: Add iacc0 register. Add "audio" instructions,
> smu, smass, smsss, slass, scutss, addss, subss.
>
> src/sim/frv/ChangeLog:
> 2003-10-01 Michael Snyder <msnyder@redhat.com>
>
> * frv.c (frvbf_shift_left_arith_saturate): New function,
> implements semantics for slass instruction.
> (frvbf_iacc_cut): New function, implements semantics for
> scutss instruction.
> * frv-sim.h: Export two new functions (above).
> * registers.c: Add iacc0h, iacc0l registers.
>
> src/sim/testsuite/ChangeLog:
> 2003-10-01 Michael Snyder <msnyder@redhat.com>
>
> * sim/frv/fr400/addss.cgs: New test file.
> * sim/frv/fr400/movgs.cgs: New test file.
> * sim/frv/fr400/movsg.cgs: New test file.
> * sim/frv/fr400/scutss.cgs: New test file.
> * sim/frv/fr400/slass.cgs: New test file.
> * sim/frv/fr400/smass.cgs: New test file.
> * sim/frv/fr400/smsss.cgs: New test file.
> * sim/frv/fr400/smu.cgs: New test file.
> * sim/frv/fr400/subss.cgs: New test file.
>
> Index: cpu/frv.cpu
> ===================================================================
> RCS file: /cvs/src/src/cpu/frv.cpu,v
> retrieving revision 1.13
> diff -p -r1.13 frv.cpu
> *** cpu/frv.cpu 24 Sep 2003 19:04:54 -0000 1.13
> --- cpu/frv.cpu 1 Oct 2003 19:14:21 -0000
> ***************
> *** 1610,1616 ****
> (hsr56 72) (hsr57 73) (hsr58 74) (hsr59 75)
> (hsr60 76) (hsr61 77) (hsr62 78) (hsr63 79)
>
> ! (ccr 256) (cccr 263) (lr 272) (lcr 273) (isr 288)
>
> (neear0 352) (neear1 353) (neear2 354) (neear3 355)
> (neear4 356) (neear5 357) (neear6 358) (neear7 359)
> --- 1610,1617 ----
> (hsr56 72) (hsr57 73) (hsr58 74) (hsr59 75)
> (hsr60 76) (hsr61 77) (hsr62 78) (hsr63 79)
>
> ! (ccr 256) (cccr 263) (lr 272) (lcr 273)
> ! (iacc0h 280) (iacc0l 281) (isr 288)
>
> (neear0 352) (neear1 353) (neear2 354) (neear3 355)
> (neear4 356) (neear5 357) (neear6 358) (neear7 359)
> ***************
> *** 1955,1960 ****
> --- 1956,1963 ----
> (define-pmacro (spr-bpcsr) (reg h-spr 2))
> (define-pmacro (spr-lr) (reg h-spr 272))
> (define-pmacro (spr-lcr) (reg h-spr 273))
> + (define-pmacro (spr-iacc0h) (reg h-spr 280))
> + (define-pmacro (spr-iacc0l) (reg h-spr 281))
> (define-pmacro (spr-sr0) (reg h-spr 768))
> (define-pmacro (spr-sr1) (reg h-spr 769))
> (define-pmacro (spr-sr2) (reg h-spr 770))
> ***************
> *** 2064,2069 ****
> --- 2067,2097 ----
> (add index 1408)) (trunc USI newval))))
> )
>
> + ; 64-bit signed accumulator. Composed of iacc0h and iacc0l registers
> + ; concatenated, but referenced more often as the composed 64 bits.
> + (define-keyword
> + (name iacc0-names)
> + (print-name h-iacc0)
> + (prefix "")
> + (values (iacc0 0))
> + )
> +
> + (define-hardware
> + (name h-iacc0)
> + (comment "64 bit signed accumulator")
> + (attrs PROFILE VIRTUAL (MACH fr400))
> + (type register DI (1))
> + (indices extern-keyword iacc0-names)
> + ; The single 64-bit integer accumulator is made up of two 32 bit
> + ; registers, iacc0h and iacc0l. We want to extract this as a
> + ; combined 64 signed bits.
> + (get (idx) (or DI (sll DI (ext DI (spr-iacc0h)) 32) (zext DI (spr-iacc0l))))
> + (set (idx newval)
> + (sequence ()
> + (set (spr-iacc0h) (trunc SI (srl newval 32)))
> + (set (spr-iacc0l) (trunc SI newval))))
> + )
> +
> ; Integer condition code registers (CCR)
> ;
> ; The individual sub registers bits of the CCR are referenced more often than
> ***************
> *** 2602,2607 ****
> --- 2630,2686 ----
> (multiply-r-r smul ext OP_00 OPE2_08 "signed multiply reg/reg")
> (multiply-r-r umul zext OP_00 OPE2_0A "unsigned multiply reg/reg")
>
> + ; Multiplication with integer accumulator IACC
> + ;
> +
> + (define-pmacro (iacc-set value)
> + (set (reg h-iacc0 0) value))
> +
> + (define-pmacro (iacc-add value)
> + (set (reg h-iacc0 0)
> + (cond DI
> + ((andif (andif (gt value 0) (gt (reg h-iacc0 0) 0))
> + (lt (sub DI #x7fffffffffffffff value) (reg h-iacc0 0)))
> + ; Positive overflow
> + (const DI #x7fffffffffffffff))
> + ((andif (andif (lt value 0) (lt (reg h-iacc0 0) 0))
> + (gt (sub DI #x8000000000000000 value) (reg h-iacc0 0)))
> + ; Negative overflow
> + (const DI #x8000000000000000))
> + (else
> + (add DI (reg h-iacc0 0) value))))
> + )
> +
> + (define-pmacro (iacc-sub value)
> + (set (reg h-iacc0 0)
> + (cond DI
> + ((andif (andif (lt value 0) (gt (reg h-iacc0 0) 0))
> + (lt (add DI #x7fffffffffffffff value) (reg h-iacc0 0)))
> + ; Positive overflow
> + (const DI #x7fffffffffffffff))
> + ((andif (andif (gt value 0) (lt (reg h-iacc0 0) 0))
> + (gt (add DI #x8000000000000000 value) (reg h-iacc0 0)))
> + ; Negative overflow
> + (const DI #x8000000000000000))
> + (else
> + (sub DI (reg h-iacc0 0) value))))
> + )
> +
> + (define-pmacro (iacc-multiply-r-r name operation op ope comment)
> + (dni name
> + (comment)
> + ((UNIT MULT-DIV) (FR400-MAJOR I-1) (MACH fr400))
> + (.str name "$pack $GRi,$GRj")
> + (+ pack (rd-null) op GRi ope GRj)
> + ((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj)))
> + ((fr400 (unit u-integer)))
> + )
> + )
> +
> + (iacc-multiply-r-r smu set OP_46 OPE1_05 "Signed multiply reg/reg/iacc")
> + (iacc-multiply-r-r smass add OP_46 OPE1_06 "Signed multiply/add reg/reg/iacc")
> + (iacc-multiply-r-r smsss sub OP_46 OPE1_07 "Signed multiply/sub reg/reg/iacc")
> +
> (define-pmacro (int-shift-r-r name op ope comment)
> (dni name
> (comment)
> ***************
> *** 2618,2623 ****
> --- 2697,2720 ----
> (int-shift-r-r srl OP_01 OPE2_0A "shift right logical reg/reg")
> (int-shift-r-r sra OP_01 OPE2_0C "shift right arith reg/reg")
>
> + (dni slass
> + "shift left arith reg/reg with saturation"
> + ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400))
> + "slass$pack $GRi,$GRj,$GRk"
> + (+ pack GRk OP_46 GRi OPE1_02 GRj)
> + (set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj))
> + ()
> + )
> +
> + (dni scutss
> + "Integer accumulator cut with saturation"
> + ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400))
> + "scutss$pack $GRj,$GRk"
> + (+ pack GRk OP_46 (rs-null) OPE1_04 GRj)
> + (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj))
> + ()
> + )
> +
> (define-pmacro (scan-semantics arg1 arg2 targ)
> (sequence ((WI tmp1) (WI tmp2))
> (set tmp1 arg1)
> ***************
> *** 2945,2950 ****
> --- 3042,3074 ----
>
> (int-arith-x-cc-r-r addxcc add OP_00 OPE2_03 "Add reg/reg, use/set carry")
> (int-arith-x-cc-r-r subxcc sub OP_00 OPE2_07 "Sub reg/reg, use/set carry")
> +
> + ; Add and subtract with saturation
> + ;
> + (define-pmacro (int-arith-ss-r-r name operation op ope comment)
> + (dni name
> + (comment)
> + ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400))
> + (.str name "$pack $GRi,$GRj,$GRk")
> + (+ pack GRk op GRi ope GRj)
> + (sequence ()
> + (set GRk (operation GRi GRj))
> + (if ((.sym operation -oflag) GRi GRj (const 0))
> + ; Overflow, saturate.
> + ; Sign of result will be
> + ; same as sign of first operand.
> + (set GRk
> + (cond SI
> + ((gt GRi 0) (const #x7fffffff))
> + ((lt GRi 0) (const #x80000000))
> + (else (const 0)))))
> + )
> + ((fr400 (unit u-integer)))
> + )
> + )
> +
> + (int-arith-ss-r-r addss add OP_46 OPE1_00 "add reg/reg, with saturation")
> + (int-arith-ss-r-r subss sub OP_46 OPE1_01 "sub reg/reg, with saturation")
>
> ; Format: INT, Logic, Shift r-simm
> ;
> Index: sim/frv/frv-sim.h
> ===================================================================
> RCS file: /cvs/src/src/sim/frv/frv-sim.h,v
> retrieving revision 1.2
> diff -p -r1.2 frv-sim.h
> *** sim/frv/frv-sim.h 12 Sep 2003 22:05:21 -0000 1.2
> --- sim/frv/frv-sim.h 1 Oct 2003 19:14:24 -0000
> *************** extern void frvbf_switch_supervisor_user
> *** 104,111 ****
> --- 104,114 ----
> extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI);
> extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
>
> + /* Insn semantics. */
> extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
> extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
> + extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
> + extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI);
>
> extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
>
> Index: sim/frv/frv.c
> ===================================================================
> RCS file: /cvs/src/src/sim/frv/frv.c,v
> retrieving revision 1.2
> diff -p -r1.2 frv.c
> *** sim/frv/frv.c 9 Sep 2003 22:28:33 -0000 1.2
> --- sim/frv/frv.c 1 Oct 2003 19:14:25 -0000
> *************** frvbf_media_cut_ss (SIM_CPU *current_cpu
> *** 1027,1032 ****
> --- 1027,1091 ----
> return frvbf_media_cut (current_cpu, acc, cut_point);
> }
>
> + /* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */
> + SI
> + frvbf_shift_left_arith_saturate (SIM_CPU *current_cpu, SI arg1, SI arg2)
> + {
> + int neg_arg1;
> +
> + /* FIXME: what to do with negative shift amt? */
> + if (arg2 <= 0)
> + return arg1;
> +
> + if (arg1 == 0)
> + return 0;
> +
> + /* Signed shift by 31 or greater saturates by definition. */
> + if (arg2 >= 31)
> + if (arg1 > 0)
> + return (SI) 0x7fffffff;
> + else
> + return (SI) 0x80000000;
> +
> + /* OK, arg2 is between 1 and 31. */
> + neg_arg1 = (arg1 < 0);
> + do {
> + arg1 <<= 1;
> + /* Check for sign bit change (saturation). */
> + if (neg_arg1 && (arg1 >= 0))
> + return (SI) 0x80000000;
> + else if (!neg_arg1 && (arg1 < 0))
> + return (SI) 0x7fffffff;
> + } while (--arg2 > 0);
> +
> + return arg1;
> + }
> +
> + /* Compute the result of int accumulator cut (SCUTSS). */
> + SI
> + frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point)
> + {
> + /* The cut point is the lower 6 bits (signed) of what we are passed. */
> + cut_point = cut_point << 25 >> 25;
> +
> + if (cut_point <= -32)
> + cut_point = -31; /* Special case for full shiftout. */
> +
> + /* Negative cuts (cannot saturate). */
> + if (cut_point < 0)
> + return acc >> (32 + -cut_point);
> +
> + /* Positive cuts will saturate if significant bits are shifted out. */
> + if (acc != ((acc << cut_point) >> cut_point))
> + if (acc >= 0)
> + return 0x7fffffff;
> + else
> + return 0x80000000;
> +
> + /* No saturate, just cut. */
> + return ((acc << cut_point) >> 32);
> + }
> +
> /* Simulate the media custom insns. */
> void
> frvbf_media_cop (SIM_CPU *current_cpu, int cop_num)
> Index: sim/frv/registers.c
> ===================================================================
> RCS file: /cvs/src/src/sim/frv/registers.c,v
> retrieving revision 1.2
> diff -p -r1.2 registers.c
> *** sim/frv/registers.c 12 Sep 2003 22:05:22 -0000 1.2
> --- sim/frv/registers.c 1 Oct 2003 19:14:40 -0000
> *************** static FRV_SPR_CONTROL_INFO frv_spr[] =
> *** 165,174 ****
> {0x00000000, 0x00000000, 0x00000000, 0x00000003, IMPL, USER}, /* LR */
> {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
>
> ! /* spr registers 274-287 are reserved */
> RESERVED,
> RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
> ! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
> RESERVED, RESERVED, RESERVED,
>
> {0xe0000021, 0x20000000, 0xe0000000, 0xffffffc2, IMPL, USER}, /* ISR */
> --- 165,177 ----
> {0x00000000, 0x00000000, 0x00000000, 0x00000003, IMPL, USER}, /* LR */
> {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
>
> ! /* spr registers 274-279 and 282-287 are reserved. */
> ! /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */
> RESERVED,
> RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
> ! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */
> ! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */
> ! RESERVED, RESERVED, RESERVED,
> RESERVED, RESERVED, RESERVED,
>
> {0xe0000021, 0x20000000, 0xe0000000, 0xffffffc2, IMPL, USER}, /* ISR */
> *************** static FRV_SPR_CONTROL_INFO fr400_spr[]
> *** 3141,3150 ****
> {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */
> {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
>
> ! /* spr registers 274-287 are reserved */
> RESERVED,
> RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
> ! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
> RESERVED, RESERVED, RESERVED,
>
> {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */
> --- 3144,3156 ----
> {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */
> {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
>
> ! /* spr registers 274-279 and 282-287 are reserved. */
> ! /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */
> RESERVED,
> RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
> ! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */
> ! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */
> ! RESERVED, RESERVED, RESERVED,
> RESERVED, RESERVED, RESERVED,
>
> {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */
> Index: sim/testsuite/sim/frv/fr400/addss.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/addss.cgs
> diff -N sim/testsuite/sim/frv/fr400/addss.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/addss.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,36 ----
> + # frv testcase for addss $GRi,$GRj,$GRk
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global add
> + add_nosaturate:
> + set_gr_immed 1,gr7
> + set_gr_immed 2,gr8
> + addss gr7,gr8,gr8
> + test_gr_immed 3,gr8
> + add_saturate_pos:
> + set_gr_limmed 0x7fff,0xffff,gr7
> + set_gr_immed 1,gr8
> + addss gr7,gr8,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> +
> + set_gr_limmed 0x4000,0x0000,gr7
> + set_gr_limmed 0x4000,0x0000,gr8
> + addss gr7,gr8,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> +
> + add_saturate_neg:
> + set_gr_limmed 0x8000,0x0000,gr7
> + set_gr_limmed 0xffff,0xffff,gr8
> + addss gr7,gr8,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> +
> + set_gr_limmed 0x8000,0x0001,gr7
> + set_gr_limmed 0x8000,0x0001,gr8
> + addss gr7,gr8,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/movgs.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/movgs.cgs
> diff -N sim/testsuite/sim/frv/fr400/movgs.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/movgs.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,50 ----
> + # frv testcase for movgs $GRj,iacc0[hl]
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global movgs
> + IACC0H:
> + set_gr_limmed 0xdead,0xbeef,gr8
> + and_spr_immed 0,iacc0h
> + movgs gr8,iacc0h
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,iacc0h
> + SPR280:
> + ; try alternate names for iacc0h
> + and_spr_immed 0,280
> + movgs gr8,spr[280] ; iacc0h is spr number 280
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,spr[280]
> +
> + IACC0L:
> + set_gr_limmed 0xdead,0xbeef,gr8
> + and_spr_immed 0,iacc0l
> + movgs gr8,iacc0l
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,iacc0l
> + SPR281:
> + ; try alternate names for iacc0l
> + and_spr_immed 0,281
> + movgs gr8,spr[281] ; iacc0l is spr number 281
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,spr[281]
> +
> + IACC0L_SPR281:
> + ; try crossing between iacc0l and spr[281]
> + and_spr_immed 0,281
> + and_spr_immed 0,iacc0l
> + movgs gr8,spr[281] ; iacc0l is spr number 281
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,iacc0l
> +
> + SPR280_IACC0H:
> + and_spr_immed 0,280
> + and_spr_immed 0,iacc0h
> + movgs gr8,iacc0h ; iacc0h is spr number 280
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,spr[280]
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/movsg.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/movsg.cgs
> diff -N sim/testsuite/sim/frv/fr400/movsg.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/movsg.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,65 ----
> + # frv testcase for movsg iacc0[hl],$GRj
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global movsg
> + Iacc0h:
> + set_spr_limmed 0xdead,0xbeef,iacc0h
> + set_gr_limmed 0,0,gr8
> + movsg iacc0h,gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,iacc0h
> + Iacc0l:
> + set_spr_limmed 0xdead,0xbeef,iacc0l
> + set_gr_limmed 0,0,gr8
> + movsg iacc0l,gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,iacc0l
> +
> + Spr280:
> + set_spr_limmed 0xdead,0xbeef,spr[280]
> + set_gr_limmed 0,0,gr8
> + movsg spr[280],gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,spr[280]
> + Spr281:
> + set_spr_limmed 0xdead,0xbeef,spr[281]
> + set_gr_limmed 0,0,gr8
> + movsg spr[281],gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,spr[281]
> +
> + Iacc0h_spr280:
> + set_spr_limmed 0xdead,0xbeef,spr[280]
> + set_spr_limmed 0xdead,0xbeef,iacc0h
> + set_gr_limmed 0,0,gr8
> + movsg iacc0h,gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,spr[280]
> + Iacc0l_spr281:
> + set_spr_limmed 0xdead,0xbeef,spr[281]
> + set_spr_limmed 0xdead,0xbeef,iacc0l
> + set_gr_limmed 0,0,gr8
> + movsg iacc0l,gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,spr[281]
> +
> + Spr280_iacc0h:
> + set_spr_limmed 0xdead,0xbeef,spr[280]
> + set_spr_limmed 0xdead,0xbeef,iacc0h
> + set_gr_limmed 0,0,gr8
> + movsg spr[280],gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,iacc0h
> + Spr281_iacc0l:
> + set_spr_limmed 0xdead,0xbeef,spr[281]
> + set_spr_limmed 0xdead,0xbeef,iacc0l
> + set_gr_limmed 0,0,gr8
> + movsg spr[281],gr8
> + test_gr_limmed 0xdead,0xbeef,gr8
> + test_spr_limmed 0xdead,0xbeef,iacc0l
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/scutss.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/scutss.cgs
> diff -N sim/testsuite/sim/frv/fr400/scutss.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/scutss.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,642 ----
> + # frv testcase for scutss $FRj,$FRk
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global scutss
> + scutss:
> + set_spr_immed 0xffffffe7,iacc0h
> + set_spr_immed 0x89abcdef,iacc0l
> +
> + set_gr_immed 0,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffe7,gr11
> +
> + set_gr_immed 1,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffcf,gr11
> +
> + set_gr_immed 2,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xff9e,gr11
> +
> + set_gr_immed 3,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xff3c,gr11
> +
> + set_gr_immed 4,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfe78,gr11
> +
> + set_gr_immed 5,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfcf1,gr11
> +
> + set_gr_immed 6,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xf9e2,gr11
> +
> + set_gr_immed 7,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xf3c4,gr11
> +
> + set_gr_immed 8,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xe789,gr11
> +
> + set_gr_immed 9,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xcf13,gr11
> +
> + set_gr_immed 10,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0x9e26,gr11
> +
> + set_gr_immed 11,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0x3c4d,gr11
> +
> + set_gr_immed 12,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfffe,0x789a,gr11
> +
> + set_gr_immed 13,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfffc,0xf135,gr11
> +
> + set_gr_immed 14,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfff9,0xe26a,gr11
> +
> + set_gr_immed 15,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfff3,0xc4d5,gr11
> +
> + set_gr_immed 16,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffe7,0x89ab,gr11
> +
> + set_gr_immed 17,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffcf,0x1357,gr11
> +
> + set_gr_immed 18,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xff9e,0x26af,gr11
> +
> + set_gr_immed 19,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xff3c,0x4d5e,gr11
> +
> + set_gr_immed 20,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfe78,0x9abc,gr11
> +
> + set_gr_immed 21,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfcf1,0x3579,gr11
> +
> + set_gr_immed 22,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xf9e2,0x6af3,gr11
> +
> + set_gr_immed 23,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xf3c4,0xd5e6,gr11
> +
> + set_gr_immed 24,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xe789,0xabcd,gr11
> +
> + set_gr_immed 25,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xcf13,0x579b,gr11
> +
> + set_gr_immed 26,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x9e26,0xaf37,gr11
> +
> + set_gr_immed 27,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 28,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 29,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 30,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 31,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 32,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 33,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 34,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 35,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 36,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 37,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 38,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 39,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 40,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 41,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 42,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 43,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 44,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 45,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 46,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 47,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 48,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 49,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 50,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 51,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 52,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 53,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 54,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 55,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 56,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 57,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 58,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 59,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 60,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 61,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 62,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 63,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11
> +
> + set_gr_immed 64,gr10 ; same as -64
> + scutss gr10,gr11
> + test_gr_immed -1,gr11
> +
> + set_gr_immed 128,gr10 ; same as 0
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffe7,gr11
> +
> + .global scutss2
> + scutss2:
> + set_spr_immed 0xe789abcd,iacc0h
> + set_spr_immed 0xefa5a5a5,iacc0l
> +
> + set_gr_limmed 0xffff,0xffff,gr10 ; -1
> + scutss gr10,gr11
> + test_gr_limmed 0xf3c4,0xd5e6,gr11
> +
> + set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter)
> + scutss gr10,gr11
> + test_gr_limmed 0xf9e2,0x6af3,gr11
> +
> + set_gr_immed -3,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfcf1,0x3579,gr11
> +
> + set_gr_immed -4,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfe78,0x9abc,gr11
> +
> + set_gr_immed -5,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xff3c,0x4d5e,gr11
> +
> + set_gr_immed -6,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xff9e,0x26af,gr11
> +
> + set_gr_immed -7,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffcf,0x1357,gr11
> +
> + set_gr_immed -8,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffe7,0x89ab,gr11
> +
> + set_gr_immed -9,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfff3,0xc4d5,gr11
> +
> + set_gr_immed -10,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfff9,0xe26a,gr11
> +
> + set_gr_immed -11,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfffc,0xf135,gr11
> +
> + set_gr_immed -12,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfffe,0x789a,gr11
> +
> + set_gr_immed -13,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0x3c4d,gr11
> +
> + set_gr_immed -14,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0x9e26,gr11
> +
> + set_gr_immed -15,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xcf13,gr11
> +
> + set_gr_immed -16,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xe789,gr11
> +
> + set_gr_immed -17,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xf3c4,gr11
> +
> + set_gr_immed -18,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xf9e2,gr11
> +
> + set_gr_immed -19,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfcf1,gr11
> +
> + set_gr_immed -20,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfe78,gr11
> +
> + set_gr_immed -21,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xff3c,gr11
> +
> + set_gr_immed -22,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xff9e,gr11
> +
> + set_gr_immed -23,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffcf,gr11
> +
> + set_gr_immed -24,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffe7,gr11
> +
> + set_gr_immed -25,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfff3,gr11
> +
> + set_gr_immed -26,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfff9,gr11
> +
> + set_gr_immed -27,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfffc,gr11
> +
> + set_gr_immed -28,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xfffe,gr11
> +
> + set_gr_immed -29,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffff,gr11
> +
> + set_gr_immed -30,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffff,gr11
> +
> + set_gr_immed -31,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffff,gr11
> +
> + set_gr_immed -32,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffff,gr11
> +
> + set_gr_limmed 0,64,gr10 ; same as -32
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffff,gr11
> +
> + set_spr_immed 0x6789abcd,iacc0h
> + set_spr_immed 0xefa5a5a5,iacc0l
> +
> + set_gr_limmed 0xffff,0xffff,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x33c4,0xd5e6,gr11
> +
> + set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter)
> + scutss gr10,gr11
> + test_gr_limmed 0x19e2,0x6af3,gr11
> +
> + set_gr_immed -3,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0cf1,0x3579,gr11
> +
> + set_gr_immed -4,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0678,0x9abc,gr11
> +
> + set_gr_immed -5,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x033c,0x4d5e,gr11
> +
> + set_gr_immed -6,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x019e,0x26af,gr11
> +
> + set_gr_immed -7,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x00cf,0x1357,gr11
> +
> + set_gr_immed -8,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0067,0x89ab,gr11
> +
> + set_gr_immed -9,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0033,0xc4d5,gr11
> +
> + set_gr_immed -10,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0019,0xe26a,gr11
> +
> + set_gr_immed -11,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x000c,0xf135,gr11
> +
> + set_gr_immed -12,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0006,0x789a,gr11
> +
> + set_gr_immed -13,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0003,0x3c4d,gr11
> +
> + set_gr_immed -14,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0001,0x9e26,gr11
> +
> + set_gr_immed -15,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0xcf13,gr11
> +
> + set_gr_immed -16,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x6789,gr11
> +
> + set_gr_immed -17,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x33c4,gr11
> +
> + set_gr_immed -18,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x19e2,gr11
> +
> + set_gr_immed -19,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0cf1,gr11
> +
> + set_gr_immed -20,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0678,gr11
> +
> + set_gr_immed -21,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x033c,gr11
> +
> + set_gr_immed -22,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x019e,gr11
> +
> + set_gr_immed -23,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x00cf,gr11
> +
> + set_gr_immed -24,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0067,gr11
> +
> + set_gr_immed -25,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0033,gr11
> +
> + set_gr_immed -26,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0019,gr11
> +
> + set_gr_immed -27,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x000c,gr11
> +
> + set_gr_immed -28,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0006,gr11
> +
> + set_gr_immed -29,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0003,gr11
> +
> + set_gr_immed -30,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0001,gr11
> +
> + set_gr_immed -31,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0000,gr11
> +
> + set_gr_immed -32,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0000,gr11
> +
> + set_gr_immed 64,gr10 ; same as -32
> + scutss gr10,gr11
> + test_gr_limmed 0x0000,0x0000,gr11
> +
> + ; Examples from the customer (modified for iacc0)
> + set_spr_immed 0xffffffff,iacc0h
> + set_spr_immed 0xffe00000,iacc0l
> +
> + set_gr_limmed 0,16,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffe0,gr11
> +
> + set_gr_limmed 0,17,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xffc0,gr11
> +
> + set_gr_limmed 0,18,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xffff,0xff80,gr11
> +
> + set_spr_immed 0,iacc0h
> + set_spr_immed 0x003fffff,iacc0l
> +
> + set_gr_limmed 0,40,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x3fff,0xff00,gr11
> +
> + set_gr_limmed 0,41,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x7fff,0xfe00,gr11
> +
> + set_spr_immed 0x7f,iacc0h
> + set_spr_immed 0xffe00000,iacc0l
> +
> + set_gr_limmed 0,40,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
> +
> + set_gr_limmed 0,41,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
> +
> + set_gr_limmed 0,42,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
> +
> + set_spr_immed 0x08,iacc0h
> + set_spr_immed 0x003fffff,iacc0l
> +
> + set_gr_limmed 0,40,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
> +
> + set_gr_limmed 0,41,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x7fff,0xffff,gr11 ; saturated
> +
> + set_spr_immed 0xffffffff,iacc0h
> + set_spr_immed 0xefe00000,iacc0l
> +
> + set_gr_limmed 0,40,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11 ; saturated
> +
> + set_gr_limmed 0,41,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11 ; saturated
> +
> + set_gr_limmed 0,42,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11 ; saturated
> +
> + set_spr_immed 0x80000000,iacc0h
> + set_spr_immed 0x003fffff,iacc0l
> +
> + set_gr_limmed 0,16,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11 ; saturated
> +
> + set_gr_limmed 0,17,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x8000,0x0000,gr11 ; saturated
> +
> + set_spr_immed 0xaf5a5a5a,iacc0h
> + set_spr_immed 0x5a5a5a5a,iacc0l
> +
> + set_gr_limmed 0xffff,0xfffc,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0xfaf5,0xa5a5,gr11
> +
> + set_spr_immed 0x2f5a5a5a,iacc0h
> + set_spr_immed 0x5a5a5a5a,iacc0l
> +
> + set_gr_limmed 0xffff,0xfff9,gr10
> + scutss gr10,gr11
> + test_gr_limmed 0x005e,0xb4b4,gr11
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/slass.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/slass.cgs
> diff -N sim/testsuite/sim/frv/fr400/slass.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/slass.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,104 ----
> + # frv testcase for slass $GRi,$GRj,$GRk
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global sll
> + slass0:
> + set_gr_immed 0,gr7 ; Shift by 0
> + set_gr_immed 2,gr8
> + slass gr8,gr7,gr6
> + test_gr_immed 2,gr8
> + test_gr_immed 0,gr7
> + test_gr_immed 2,gr6
> + slass1:
> + set_gr_immed 1,gr7 ; Shift by 1
> + set_gr_immed 2,gr8
> + slass gr8,gr7,gr6
> + test_gr_immed 2,gr8
> + test_gr_immed 1,gr7
> + test_gr_immed 4,gr6
> +
> + slass2:
> + set_gr_immed 31,gr7 ; Shift 1 by 31
> + set_gr_immed 1,gr8
> + slass gr8,gr7,gr6
> + test_gr_immed 1,gr8
> + test_gr_immed 31,gr7
> + test_gr_limmed 0x7fff,0xffff,gr6
> +
> + slass3:
> + set_gr_immed 31,gr7 ; Shift -1 by 31
> + set_gr_immed -1,gr8
> + slass gr8,gr7,gr6
> + test_gr_immed -1,gr8
> + test_gr_immed 31,gr7
> + test_gr_limmed 0x8000,0x0000,gr6
> +
> + slass4:
> + set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14
> + set_gr_limmed 0xffff,0x0000,gr8
> + slass gr8,gr7,gr6
> + test_gr_limmed 0xffff,0x0000,gr8
> + test_gr_immed 14,gr7
> + test_gr_limmed 0xc000,0x0000,gr6
> +
> + slass5:
> + set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15
> + set_gr_limmed 0xffff,0x0000,gr8
> + slass gr8,gr7,gr6
> + test_gr_limmed 0xffff,0x0000,gr8
> + test_gr_immed 15,gr7
> + test_gr_limmed 0x8000,0x0000,gr6
> +
> + slass6:
> + set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20
> + set_gr_limmed 0xffff,0x0000,gr8
> + slass gr8,gr7,gr6
> + test_gr_limmed 0xffff,0x0000,gr8
> + test_gr_immed 20,gr7
> + test_gr_limmed 0x8000,0x0000,gr6
> +
> + slass7:
> + set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14
> + set_gr_limmed 0x0000,0xffff,gr8
> + slass gr8,gr7,gr6
> + test_gr_limmed 0x0000,0xffff,gr8
> + test_gr_immed 14,gr7
> + test_gr_limmed 0x3fff,0xc000,gr6
> +
> + slass8:
> + set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15
> + set_gr_limmed 0x0000,0xffff,gr8
> + slass gr8,gr7,gr6
> + test_gr_limmed 0x0000,0xffff,gr8
> + test_gr_immed 15,gr7
> + test_gr_limmed 0x7fff,0x8000,gr6
> +
> + slass9:
> + set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20
> + set_gr_limmed 0x0000,0xffff,gr8
> + slass gr8,gr7,gr6
> + test_gr_limmed 0x0000,0xffff,gr8
> + test_gr_immed 20,gr7
> + test_gr_limmed 0x7fff,0xffff,gr6
> +
> + slass10:
> + set_gr_immed 30,gr7 ; Shift 1 by 30
> + set_gr_immed 1,gr8
> + slass gr8,gr7,gr6
> + test_gr_immed 1,gr8
> + test_gr_immed 30,gr7
> + test_gr_limmed 0x4000,0x0000,gr6
> +
> + slass11:
> + set_gr_immed 30,gr7 ; Shift -1 by 30
> + set_gr_immed -1,gr8
> + slass gr8,gr7,gr6
> + test_gr_immed -1,gr8
> + test_gr_immed 30,gr7
> + test_gr_limmed 0xc000,0000,gr6
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/smass.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/smass.cgs
> diff -N sim/testsuite/sim/frv/fr400/smass.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/smass.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,359 ----
> + # frv testcase for smass $GRi,$GRj
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global smass
> + smass1:
> + ; Positive operands
> + set_gr_immed 3,gr7 ; multiply small numbers
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 3,gr7
> + test_gr_immed 2,gr8
> + test_spr_immed 7,iacc0l ; result 3*2+1
> + test_spr_immed 0,iacc0h
> + smass2:
> + set_gr_immed 1,gr7 ; multiply by 1
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 1,gr7
> + test_gr_immed 2,gr8
> + test_spr_immed 3,iacc0l ; result 1*2+1
> + test_spr_immed 0,iacc0h
> + smass3:
> + set_gr_immed 2,gr7 ; multiply by 1
> + set_gr_immed 1,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 1,gr8
> + test_gr_immed 2,gr7
> + test_spr_immed 3,iacc0l ; result 2*1+1
> + test_spr_immed 0,iacc0h
> + smass4:
> + set_gr_immed 0,gr7 ; multiply by 0
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_immed 0,gr7
> + test_spr_immed 1,iacc0l ; result 0*2+1
> + test_spr_immed 0,iacc0h
> + smass5:
> + set_gr_immed 2,gr7 ; multiply by 0
> + set_gr_immed 0,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 0,gr8
> + test_gr_immed 2,gr7
> + test_spr_immed 1,iacc0l ; result 2*0+1
> + test_spr_immed 0,iacc0h
> + smass6:
> + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_limmed 0x3fff,0xffff,gr7
> + test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1
> + test_spr_immed 0,iacc0h
> + smass7:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1
> + test_spr_immed 0,iacc0h
> + smass8:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
> + set_gr_immed 4,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 4,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_immed 1,iacc0l ; 40000000*4+1
> + test_spr_immed 1,iacc0h
> + smass9:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1
> + test_spr_limmed 0x3fff,0xffff,iacc0h
> + smass10:
> + ; Mixed operands
> + set_gr_immed -3,gr7 ; multiply small numbers
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_immed -3,gr7
> + test_spr_immed -5,iacc0l ; -3*2+1
> + test_spr_immed -1,iacc0h
> + smass11:
> + set_gr_immed 3,gr7 ; multiply small numbers
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 3,gr7
> + test_spr_immed -5,iacc0l ; 3*-2+1
> + test_spr_immed -1,iacc0h
> + smass12:
> + set_gr_immed 1,gr7 ; multiply by 1
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 1,gr7
> + test_spr_immed -1,iacc0l ; 1*-2+1
> + test_spr_immed -1,iacc0h
> + smass13:
> + set_gr_immed -2,gr7 ; multiply by 1
> + set_gr_immed 1,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 1,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed -1,iacc0l ; -2*1+1
> + test_spr_immed -1,iacc0h
> + smass14:
> + set_gr_immed 0,gr7 ; multiply by 0
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 0,gr7
> + test_spr_immed 1,iacc0l ; 0*-2+1
> + test_spr_immed 0,iacc0h
> + smass15:
> + set_gr_immed -2,gr7 ; multiply by 0
> + set_gr_immed 0,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed 0,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed 1,iacc0l ; -2*0+1
> + test_spr_immed 0,iacc0h
> + smass16:
> + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x2000,0x0001,gr7
> + test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smass17:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smass18:
> + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x4000,0x0001,gr7
> + test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smass19:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
> + set_gr_immed -4,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -4,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smass20:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1
> + test_spr_limmed 0xc000,0x0000,iacc0h
> + smass21:
> + ; Negative operands
> + set_gr_immed -3,gr7 ; multiply small numbers
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed -3,gr7
> + test_spr_immed 7,iacc0l ; -3*-2+1
> + test_spr_immed 0,iacc0h
> + smass22:
> + set_gr_immed -1,gr7 ; multiply by 1
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed -1,gr7
> + test_spr_immed 3,iacc0l ; -1*-2+1
> + test_spr_immed 0,iacc0h
> + smass23:
> + set_gr_immed -2,gr7 ; multiply by 1
> + set_gr_immed -1,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -1,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed 3,iacc0l ; -2*-1+1
> + test_spr_immed 0,iacc0h
> + smass24:
> + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0xc000,0x0001,gr7
> + test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1
> + test_spr_immed 0,iacc0h
> + smass25:
> + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0xc000,0x0000,gr7
> + test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1
> + test_spr_immed 0,iacc0h
> + smass26:
> + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
> + set_gr_immed -4,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_immed -4,gr8
> + test_gr_limmed 0xc000,0x0000,gr7
> + test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1
> + test_spr_immed 1,iacc0h
> + smass27:
> + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
> + set_gr_limmed 0x8000,0x0001,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_limmed 0x8000,0x0001,gr8
> + test_gr_limmed 0x8000,0x0001,gr7
> + test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1
> + test_spr_limmed 0x3fff,0xffff,iacc0h
> + smass28:
> + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smass gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x8000,0x0000,gr7
> + test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1
> + test_spr_limmed 0x4000,0x0000,iacc0h
> +
> + smass29:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos)
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_limmed 0xffff,0xfffe,iacc0l
> + set_spr_limmed 0x4000,0x0000,iacc0h
> + smass gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
> + test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe
> +
> + smass30:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos)
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_limmed 0xffff,0xffff,iacc0l
> + set_spr_limmed 0x4000,0x0000,iacc0h
> + smass gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
> + test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff
> +
> + smass31:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos)
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_limmed 0xffff,0xffff,iacc0l
> + set_spr_limmed 0x7fff,0xffff,iacc0h
> + smass gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+
> + test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff
> +
> + smass32:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg)
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_limmed 0x8000,0x0000,iacc0l
> + set_spr_limmed 0xbfff,0xffff,iacc0h
> + smass gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
> + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000
> +
> + smass33:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg)
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_limmed 0x7fff,0xffff,iacc0l
> + set_spr_limmed 0xbfff,0xffff,iacc0h
> + smass gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
> + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff
> +
> + smass34:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg)
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_limmed 0x0000,0x0000,iacc0l
> + set_spr_limmed 0x8000,0x0000,iacc0h
> + smass gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
> + test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/smsss.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/smsss.cgs
> diff -N sim/testsuite/sim/frv/fr400/smsss.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/smsss.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,354 ----
> + # frv testcase for smsss $GRi,$GRj
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global smsss
> + smsss1:
> + ; Positive operands
> + set_gr_immed 3,gr7 ; multiply small numbers
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 7,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 3,gr7
> + test_gr_immed 2,gr8
> + test_spr_immed 1,iacc0l ; result 7-3*2
> + test_spr_immed 0,iacc0h
> + smsss2:
> + set_gr_immed 1,gr7 ; multiply by 1
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 3,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 1,gr7
> + test_gr_immed 2,gr8
> + test_spr_immed 1,iacc0l ; result 3-1*2
> + test_spr_immed 0,iacc0h
> + smsss3:
> + set_gr_immed 2,gr7 ; multiply by 1
> + set_gr_immed 1,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 3,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 1,gr8
> + test_gr_immed 2,gr7
> + test_spr_immed 1,iacc0l ; result 3-2*1
> + test_spr_immed 0,iacc0h
> + smsss4:
> + set_gr_immed 0,gr7 ; multiply by 0
> + set_gr_immed 2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_immed 0,gr7
> + test_spr_immed 1,iacc0l ; result 1-0*2
> + test_spr_immed 0,iacc0h
> + smsss5:
> + set_gr_immed 2,gr7 ; multiply by 0
> + set_gr_immed 0,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 0,gr8
> + test_gr_immed 2,gr7
> + test_spr_immed 1,iacc0l ; result 1-2*0
> + test_spr_immed 0,iacc0h
> + smsss6:
> + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
> + set_gr_immed 2,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_immed -1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_limmed 0x3fff,0xffff,gr7
> + test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2
> + test_spr_immed -1,iacc0h
> + smsss7:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
> + set_gr_immed 2,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_limmed 0x8000,0x0001,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2
> + test_spr_immed -1,iacc0h
> + smsss8:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
> + set_gr_immed 4,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 4,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4
> + test_spr_immed -2,iacc0h
> + smsss9:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_limmed 0x7fff,0xffff,iacc0h
> + set_spr_immed -1,iacc0l
> + smsss gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff
> + test_spr_limmed 0x4000,0x0000,iacc0h
> + smsss10:
> + ; Mixed operands
> + set_gr_immed -3,gr7 ; multiply small numbers
> + set_gr_immed 2,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_immed -5,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_immed -3,gr7
> + test_spr_immed 1,iacc0l ; -5-(-3*2)
> + test_spr_immed 0,iacc0h
> + smsss11:
> + set_gr_immed 3,gr7 ; multiply small numbers
> + set_gr_immed -2,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_immed -5,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 3,gr7
> + test_spr_immed 1,iacc0l ; -5-(3*-2)
> + test_spr_immed 0,iacc0h
> + smsss12:
> + set_gr_immed 1,gr7 ; multiply by 1
> + set_gr_immed -2,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_immed -1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 1,gr7
> + test_spr_immed 1,iacc0l ; -1-(1*-2)
> + test_spr_immed 0,iacc0h
> + smsss13:
> + set_gr_immed -2,gr7 ; multiply by 1
> + set_gr_immed 1,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_immed -1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 1,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed 1,iacc0l ; -1-(-2*1)
> + test_spr_immed 0,iacc0h
> + smsss14:
> + set_gr_immed 0,gr7 ; multiply by 0
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 0,gr7
> + test_spr_immed 1,iacc0l ; 1-(0*-2)
> + test_spr_immed 0,iacc0h
> + smsss15:
> + set_gr_immed -2,gr7 ; multiply by 0
> + set_gr_immed 0,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 0,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed 1,iacc0l ; 1-(-2*0)
> + test_spr_immed 0,iacc0h
> + smsss16:
> + set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_limmed 0x3fff,0xffff,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x2000,0x0000,gr7
> + test_spr_limmed 0x7fff,0xffff,iacc0l
> + test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2
> + smsss17:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2
> + test_spr_immed 0,iacc0h
> + smsss18:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + set_spr_immed -1,iacc0h
> + set_spr_immed -1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x7fff,0xffff,iacc0l
> + test_spr_immed 0,iacc0h ; -1-40000000*-2
> + smsss19:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
> + set_gr_immed -4,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -4,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_immed 1,iacc0l ; 200000001-(40000000*-4)
> + test_spr_immed 1,iacc0h
> + smsss20:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_limmed 0xbfff,0xffff,iacc0h
> + set_spr_limmed 0x0000,0x0001,iacc0l
> + smsss gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff)
> + test_spr_limmed 0x8000,0x0000,iacc0h
> + smsss21:
> + ; Negative operands
> + set_gr_immed -3,gr7 ; multiply small numbers
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 7,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed -3,gr7
> + test_spr_immed 1,iacc0l ; 7-(-3*-2)
> + test_spr_immed 0,iacc0h
> + smsss22:
> + set_gr_immed -1,gr7 ; multiply by 1
> + set_gr_immed -2,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 3,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed -1,gr7
> + test_spr_immed 1,iacc0l ; 3-(-1*-2)
> + test_spr_immed 0,iacc0h
> + smsss23:
> + set_gr_immed -2,gr7 ; multiply by 1
> + set_gr_immed -1,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_immed 3,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -1,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed 1,iacc0l ; 3-(-2*-1)
> + test_spr_immed 0,iacc0h
> + smsss24:
> + set_gr_immed -32768,gr7 ; 31 bit result
> + set_gr_immed -32768,gr8
> + set_spr_immed 0,iacc0h
> + set_spr_limmed 0xbfff,0xffff,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -32768,gr8
> + test_gr_immed -32768,gr7
> + test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2)
> + test_spr_immed 0,iacc0h
> + smsss25:
> + set_gr_immed 0xffff,gr7 ; 32 bit result
> + set_gr_immed 0xffff,gr8
> + set_spr_immed 1,iacc0h
> + set_spr_limmed 0xfffe,0x0000,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 0xffff,gr8
> + test_gr_immed 0xffff,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff
> + test_spr_immed 0,iacc0h
> + smsss26:
> + set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result
> + set_gr_limmed 0x0001,0x0000,gr8
> + set_spr_immed 2,iacc0h
> + set_spr_immed 1,iacc0l
> + smsss gr7,gr8
> + test_gr_limmed 0x0001,0x0000,gr8
> + test_gr_limmed 0x0001,0x0000,gr7
> + test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000
> + test_spr_immed 1,iacc0h
> + smsss27:
> + set_gr_immed -2,gr7 ; almost max positive result
> + set_gr_immed -2,gr8
> + set_spr_limmed 0x7fff,0xffff,iacc0h
> + set_spr_limmed 0xffff,0xffff,iacc0l
> + smsss gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed -2,gr7
> + test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2)
> + test_spr_limmed 0x7fff,0xffff,iacc0h
> + smsss28:
> + set_gr_immed 0,gr7 ; max positive result
> + set_gr_immed 0,gr8
> + set_spr_limmed 0x7fff,0xffff,iacc0h
> + set_spr_limmed 0xffff,0xffff,iacc0l
> + smsss gr7,gr8
> + test_gr_immed 0,gr8
> + test_gr_immed 0,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0)
> + test_spr_limmed 0x7fff,0xffff,iacc0h
> + smsss29:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos)
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_limmed 0x4000,0x0000,iacc0h
> + set_spr_limmed 0x7fff,0xffff,iacc0l
> + smsss gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff -
> + test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff
> + smsss30:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos)
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_limmed 0x4000,0x0000,iacc0h
> + set_spr_limmed 0x8000,0x0000,iacc0l
> + smsss gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 -
> + test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff
> +
> + smsss31:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos)
> + set_gr_limmed 0x8000,0x0000,gr8
> + set_spr_limmed 0xffff,0xffff,iacc0l
> + set_spr_limmed 0x7fff,0xffff,iacc0h
> + smsss gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff -
> + test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000
> + smsss32:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg)
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_immed 1,iacc0l
> + set_spr_limmed 0xbfff,0xffff,iacc0h
> + smsss gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 -
> + test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff
> + smsss33:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg)
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_immed 0,iacc0l
> + set_spr_limmed 0xbfff,0xffff,iacc0h
> + smsss gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
> + test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff
> + smsss34:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg)
> + set_gr_limmed 0x7fff,0xffff,gr8
> + set_spr_limmed 0x0000,0x0000,iacc0l
> + set_spr_limmed 0x8000,0x0000,iacc0h
> + smsss gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000-
> + test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/smu.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/smu.cgs
> diff -N sim/testsuite/sim/frv/fr400/smu.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/smu.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,237 ----
> + # frv testcase for smu $GRi,$GRj
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global smu
> + smu1:
> + ; Positive operands
> + set_gr_immed 3,gr7 ; multiply small numbers
> + set_gr_immed 2,gr8
> + smu gr7,gr8
> + test_gr_immed 3,gr7
> + test_gr_immed 2,gr8
> + test_spr_immed 6,iacc0l
> + test_spr_immed 0,iacc0h
> + smu2:
> + set_gr_immed 1,gr7 ; multiply by 1
> + set_gr_immed 2,gr8
> + smu gr7,gr8
> + test_gr_immed 1,gr7
> + test_gr_immed 2,gr8
> + test_spr_immed 2,iacc0l
> + test_spr_immed 0,iacc0h
> + smu3:
> + set_gr_immed 2,gr7 ; multiply by 1
> + set_gr_immed 1,gr8
> + smu gr7,gr8
> + test_gr_immed 1,gr8
> + test_gr_immed 2,gr7
> + test_spr_immed 2,iacc0l
> + test_spr_immed 0,iacc0h
> + smu4:
> + set_gr_immed 0,gr7 ; multiply by 0
> + set_gr_immed 2,gr8
> + smu gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_immed 0,gr7
> + test_spr_immed 0,iacc0l
> + test_spr_immed 0,iacc0h
> + smu5:
> + set_gr_immed 2,gr7 ; multiply by 0
> + set_gr_immed 0,gr8
> + smu gr7,gr8
> + test_gr_immed 0,gr8
> + test_gr_immed 2,gr7
> + test_spr_immed 0,iacc0l
> + test_spr_immed 0,iacc0h
> + smu6:
> + set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
> + set_gr_immed 2,gr8
> + smu gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_limmed 0x3fff,0xffff,gr7
> + test_spr_limmed 0x7fff,0xfffe,iacc0l
> + test_spr_immed 0,iacc0h
> + smu7:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
> + set_gr_immed 2,gr8
> + smu gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x8000,0x0000,iacc0l
> + test_spr_immed 0,iacc0h
> + smu8:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
> + set_gr_immed 4,gr8
> + smu gr7,gr8
> + test_gr_immed 4,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_immed 0,iacc0l
> + test_spr_immed 1,iacc0h
> + smu9:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
> + set_gr_limmed 0x7fff,0xffff,gr8
> + smu gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_immed 0x00000001,iacc0l
> + test_spr_limmed 0x3fff,0xffff,iacc0h
> + smu10:
> + ; Mixed operands
> + set_gr_immed -3,gr7 ; multiply small numbers
> + set_gr_immed 2,gr8
> + smu gr7,gr8
> + test_gr_immed 2,gr8
> + test_gr_immed -3,gr7
> + test_spr_immed -6,iacc0l
> + test_spr_immed -1,iacc0h
> + smu11:
> + set_gr_immed 3,gr7 ; multiply small numbers
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 3,gr7
> + test_spr_immed -6,iacc0l
> + test_spr_immed -1,iacc0h
> + smu12:
> + set_gr_immed 1,gr7 ; multiply by 1
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 1,gr7
> + test_spr_immed -2,iacc0l
> + test_spr_immed -1,iacc0h
> + smu13:
> + set_gr_immed -2,gr7 ; multiply by 1
> + set_gr_immed 1,gr8
> + smu gr7,gr8
> + test_gr_immed 1,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed -2,iacc0l
> + test_spr_immed -1,iacc0h
> + smu14:
> + set_gr_immed 0,gr7 ; multiply by 0
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed 0,gr7
> + test_spr_immed 0,iacc0l
> + test_spr_immed 0,iacc0h
> + smu15:
> + set_gr_immed -2,gr7 ; multiply by 0
> + set_gr_immed 0,gr8
> + smu gr7,gr8
> + test_gr_immed 0,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed 0,iacc0l
> + test_spr_immed 0,iacc0h
> + smu16:
> + set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x2000,0x0001,gr7
> + test_spr_limmed 0xbfff,0xfffe,iacc0l
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smu17:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x8000,0x0000,iacc0l
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smu18:
> + set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0x4000,0x0001,gr7
> + test_spr_limmed 0x7fff,0xfffe,iacc0l
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smu19:
> + set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
> + set_gr_immed -4,gr8
> + smu gr7,gr8
> + test_gr_immed -4,gr8
> + test_gr_limmed 0x4000,0x0000,gr7
> + test_spr_limmed 0x0000,0x0000,iacc0l
> + test_spr_limmed 0xffff,0xffff,iacc0h
> + smu20:
> + set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
> + set_gr_limmed 0x8000,0x0000,gr8
> + smu gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x7fff,0xffff,gr7
> + test_spr_limmed 0x8000,0x0000,iacc0l
> + test_spr_limmed 0xc000,0x0000,iacc0h
> + smu21:
> + ; Negative operands
> + set_gr_immed -3,gr7 ; multiply small numbers
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed -3,gr7
> + test_spr_immed 6,iacc0l
> + test_spr_immed 0,iacc0h
> + smu22:
> + set_gr_immed -1,gr7 ; multiply by 1
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_immed -1,gr7
> + test_spr_immed 2,iacc0l
> + test_spr_immed 0,iacc0h
> + smu23:
> + set_gr_immed -2,gr7 ; multiply by 1
> + set_gr_immed -1,gr8
> + smu gr7,gr8
> + test_gr_immed -1,gr8
> + test_gr_immed -2,gr7
> + test_spr_immed 2,iacc0l
> + test_spr_immed 0,iacc0h
> + smu24:
> + set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0xc000,0x0001,gr7
> + test_spr_limmed 0x7fff,0xfffe,iacc0l
> + test_spr_immed 0,iacc0h
> + smu25:
> + set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
> + set_gr_immed -2,gr8
> + smu gr7,gr8
> + test_gr_immed -2,gr8
> + test_gr_limmed 0xc000,0x0000,gr7
> + test_spr_limmed 0x8000,0x0000,iacc0l
> + test_spr_immed 0,iacc0h
> + smu26:
> + set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
> + set_gr_immed -4,gr8
> + smu gr7,gr8
> + test_gr_immed -4,gr8
> + test_gr_limmed 0xc000,0x0000,gr7
> + test_spr_immed 0x00000000,iacc0l
> + test_spr_immed 1,iacc0h
> + smu27:
> + set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
> + set_gr_limmed 0x8000,0x0001,gr8
> + smu gr7,gr8
> + test_gr_limmed 0x8000,0x0001,gr8
> + test_gr_limmed 0x8000,0x0001,gr7
> + test_spr_immed 0x00000001,iacc0l
> + test_spr_limmed 0x3fff,0xffff,iacc0h
> + smu28:
> + set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
> + set_gr_limmed 0x8000,0x0000,gr8
> + smu gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> + test_gr_limmed 0x8000,0x0000,gr7
> + test_spr_immed 0x00000000,iacc0l
> + test_spr_limmed 0x4000,0x0000,iacc0h
> +
> + pass
> Index: sim/testsuite/sim/frv/fr400/subss.cgs
> ===================================================================
> RCS file: sim/testsuite/sim/frv/fr400/subss.cgs
> diff -N sim/testsuite/sim/frv/fr400/subss.cgs
> *** /dev/null 1 Jan 1970 00:00:00 -0000
> --- sim/testsuite/sim/frv/fr400/subss.cgs 1 Oct 2003 19:14:45 -0000
> ***************
> *** 0 ****
> --- 1,43 ----
> + # frv testcase for subss $GRi,$GRj,$GRk
> + # mach: fr400
> +
> + .include "../testutils.inc"
> +
> + start
> +
> + .global sub
> + sub_no_saturate:
> + set_gr_immed 1,gr7
> + set_gr_immed 2,gr8
> + subss gr8,gr7,gr8
> + test_gr_immed 1,gr8
> +
> + set_gr_immed 2,gr7
> + set_gr_immed 1,gr8
> + subss gr8,gr7,gr8
> + test_gr_limmed 0xffff,0xffff,gr8
> +
> + sub_saturate_neg:
> + set_gr_immed 1,gr7
> + set_gr_limmed 0x8000,0x0000,gr8
> + subss gr8,gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> +
> + set_gr_limmed 0x7fff,0xffff,gr7
> + set_gr_limmed 0xffff,0xfff0,gr8
> + subss gr8,gr7,gr8
> + test_gr_limmed 0x8000,0x0000,gr8
> +
> + sub_saturate_pos:
> + set_gr_limmed 0xffff,0xffff,gr7
> + set_gr_limmed 0x7fff,0xffff,gr8
> + subss gr8,gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> +
> + set_gr_immed 0x0010,gr8
> + set_gr_limmed 0x8000,0x0000,gr7
> + subss gr8,gr7,gr8
> + test_gr_limmed 0x7fff,0xffff,gr8
> +
> +
> + pass
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