[commit] FRV Simulator Cycle Accurate Cache

[Dave Brolley]

Hi,

I've committed this patch which adds a check for higher priority 
requests in the same cache pipeline when checking for address 
interference. This addresses a problem which occurs when a request gets 
requeued because the wait registers (WARS, BARS, NARS) are full. In some 
cases the requeued request was getting requeued behind a lower priority 
request for the same cache line which was behind it originally. This 
change correctly causes the lower priority request to also be requeued.

Dave
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