[PATCH] Support Altivec tests on Mac OS X
Klee Dienes
klee@apple.com
Sun Oct 6 21:59:00 GMT 2002
Daniel Jacobowitz was kind enough to point out that my macro hackery
for the non-__APPLE__ case was completely bogus. I'd tried to be
clever and avoid using the varargs extensions in GCC, and forgot that
the Debian/PPC machine I was testing on had been hacked to define
__APPLE__ for some other stuff I was playing around with, and so it was
never getting tested.
To avoid having to do macro hackery, I implemented VDECL as VDECL4/8/16
and just specified the appropriate one for each declaration.
A revised patch follows:
2002-10-06 Klee Dienes <kdienes@apple.com>
* gdb.arch/altivec-abi.c: Conditionalize inclusion of altivec.h.
New macros, VDECL4/8/16, to handle differences in the OS X
initialization syntax (Mac OS X should support the {}-style
syntax, but doesn't in all cases due to a compiler issue).
Explicitly specify signed vs. unsiged for int, short, and
char, to placate the OS X compiler. Explicitly set vrsave to
0xfffffff on OS X.
* gdb.arch/altivec-regs.c: Conditionalize inclusion of
altivec.h.
Explicitly setvrsave to 0xfffffff on Mac OS X.
* gdb.arch/altivec-abi.exp: Add test for powerpc-apple-* when
detecting Altivec support. Paramterize the compile flags
needed for Altivec support.
* gdb.arch/altivec-regs.exp: Add test for powerpc-apple-* when
detecting Altivec support. Paramterize the compile flags
needed for Altivec support. Paramterize the base of the
vector register names (Apple uses v<n>, not vr<n>). Rename
vector_register to hex_register. Expect results from 'info
reg' in decimal format; also add a test for 'print /x' to get
the
registers in hex format. Comment out the test for "info powerpc
altivec" (the function was removed recently).
Index: altivec-abi.c
===================================================================
RCS file:
/cvs/Darwin/src/live/cygnus/src/gdb/testsuite/gdb.arch/altivec-abi.c,v
retrieving revision 1.1.1.1
retrieving revision 1.3
diff -u -r1.1.1.1 -r1.3
--- altivec-abi.c 2002/08/11 23:27:05 1.1.1.1
+++ altivec-abi.c 2002/10/07 04:55:38 1.3
@@ -1,20 +1,32 @@
+#ifndef __APPLE__
#include <altivec.h>
+#endif
+
+#ifdef __APPLE__
+#define VDECL4(type, v1, v2, v3, v4) (type) (v1, v2, v3, v4)
+#define VDECL8(type, v1, v2, v3, v4, v5, v6, v7, v8) (type) (v1, v2,
v3, v4, v5, v6, v7, v8)
+#define VDECL16(type, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11,
v12, v13, v14, v15, v16) (type) (v1, v2, v3, v4, v5, v6, v7, v8, v9,
v10, v11, v12, v13, v14, v15, v16)
+#else
+#define VDECL4(type, v1, v2, v3, v4) ((type) {v1, v2, v3, v4})
+#define VDECL8(type, v1, v2, v3, v4, v5, v6, v7, v8) ((type) {v1, v2,
v3, v4, v5, v6, v7, v8})
+#define VDECL16(type, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11,
v12, v13, v14, v15, v16) ((type) {v1, v2, v3, v4, v5, v6, v7, v8, v9,
v10, v11, v12, v13, v14, v15, v16})
+#endif
-vector short vshort = {111, 222, 333, 444, 555, 666, 777,
888};
-vector unsigned short vushort = {100, 200, 300, 400, 500, 600, 700,
800};
-vector int vint = {-10, -20, -30, -40};
-vector unsigned int vuint = {1111, 2222, 3333, 4444};
-vector char vchar =
{'a','b','c','d','e','f','g','h','i','l','m','n','o','p','q','r'};
-vector unsigned char vuchar =
{'A','B','C','D','E','F','G','H','I','L','M','N','O','P','Q','R'};
-vector float vfloat = {1.25, 3.75, 5.5, 1.25};
-
-vector short vshort_d = {0,0,0,0,0,0,0,0};
-vector unsigned short vushort_d = {0,0,0,0,0,0,0,0};
-vector int vint_d = {0,0,0,0};
-vector unsigned int vuint_d = {0,0,0,0};
-vector char vchar_d =
{'z','z','z','z','z','z','z','z','z','z','z','z','z','z','z','z'};
-vector unsigned char vuchar_d =
{'Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z'};
-vector float vfloat_d = {1.0, 1.0, 1.0, 1.0};
+vector short vshort = VDECL8 (vector signed short, 111,
222, 333, 444, 555, 666, 777, 888);
+vector unsigned short vushort = VDECL8 (vector unsigned short, 100,
200, 300, 400, 500, 600, 700, 800);
+vector signed int vint = VDECL4 (vector signed int, -10, -20,
-30, -40);
+vector unsigned int vuint = VDECL4 (vector unsigned int, 1111,
2222, 3333, 4444);
+vector signed char vchar = VDECL16 (vector signed char,
'a','b','c','d','e','f','g','h','i','l','m','n','o','p','q','r');
+vector unsigned char vuchar = VDECL16 (vector unsigned char,
'A','B','C','D','E','F','G','H','I','L','M','N','O','P','Q','R');
+vector float vfloat = VDECL4 (vector float, 1.25, 3.75,
5.5, 1.25);
+
+vector signed short vshort_d = VDECL8 (vector signed short, 0, 0,
0, 0, 0, 0, 0, 0);
+vector unsigned short vushort_d = VDECL8 (vector unsigned short, 0,
0, 0, 0, 0, 0, 0, 0);
+vector signed int vint_d = VDECL4 (vector signed int, 0, 0,
0, 0);
+vector unsigned int vuint_d = VDECL4 (vector unsigned int, 0, 0,
0, 0);
+vector signed char vchar_d = VDECL16 (vector signed char,
'z','z','z','z','z','z','z','z','z','z','z','z','z','z','z','z');
+vector unsigned char vuchar_d = VDECL16 (vector unsigned char,
'Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z','Z');
+vector float vfloat_d = VDECL4 (vector float, 1.0, 1.0,
1.0, 1.0);
struct test_vec_struct
{
@@ -26,10 +38,10 @@
static vector signed short test4[4] =
{
- (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8},
- (vector signed short) {11, 12, 13, 14, 15, 16, 17, 18},
- (vector signed short) {21, 22, 23, 24, 25, 26, 27, 28},
- (vector signed short) {31, 32, 33, 34, 35, 36, 37, 38}
+ VDECL8 (vector signed short, 1, 2, 3, 4, 5, 6, 7, 8),
+ VDECL8 (vector signed short, 11, 12, 13, 14, 15, 16, 17, 18),
+ VDECL8 (vector signed short, 21, 22, 23, 24, 25, 26, 27, 28),
+ VDECL8 (vector signed short, 31, 32, 33, 34, 35, 36, 37, 38)
};
void
@@ -46,41 +58,41 @@
matrix[2] = vec_add (matrix[2], matrix[3]);
}
-vector int
+vector signed int
vec_func (vector short vshort_f, /* goes in v2 */
vector unsigned short vushort_f, /* goes in v3 */
- vector int vint_f, /* goes in v4 */
+ vector signed int vint_f, /* goes in v4 */
vector unsigned int vuint_f, /* goes in v5 */
- vector char vchar_f, /* goes in v6 */
+ vector signed char vchar_f, /* goes in v6 */
vector unsigned char vuchar_f, /* goes in v7 */
vector float vfloat_f, /* goes in v8 */
- vector short x_f, /* goes in v9 */
- vector int y_f, /* goes in v10 */
- vector char a_f, /* goes in v11 */
+ vector signed short x_f, /* goes in v9 */
+ vector signed int y_f, /* goes in v10 */
+ vector signed char a_f, /* goes in v11 */
vector float b_f, /* goes in v12 */
vector float c_f, /* goes in v13 */
- vector int intv_on_stack_f)
+ vector signed int intv_on_stack_f)
{
- vector int vint_res;
+ vector signed int vint_res;
vector unsigned int vuint_res;
- vector short vshort_res;
+ vector signed short vshort_res;
vector unsigned short vushort_res;
- vector char vchar_res;
+ vector signed char vchar_res;
vector float vfloat_res;
vector unsigned char vuchar_res;
vint_res = vec_add (vint_f, intv_on_stack_f);
vint_res = vec_add (vint_f, y_f);
- vuint_res = vec_add (vuint_f, ((vector unsigned int) {5,6,7,8}));
+ vuint_res = vec_add (vuint_f, VDECL4 (vector unsigned int, 5, 6,
7, 8));
vshort_res = vec_add (vshort_f, x_f);
vushort_res = vec_add (vushort_f,
- ((vector unsigned short)
{1,2,3,4,5,6,7,8}));
+ VDECL8 (vector unsigned short, 1, 2, 3, 4,
5, 6, 7, 8));
vchar_res = vec_add (vchar_f, a_f);
vfloat_res = vec_add (vfloat_f, b_f);
- vfloat_res = vec_add (c_f, ((vector float) {1.1,1.1,1.1,1.1}));
+ vfloat_res = vec_add (c_f, VDECL4 (vector float, 1.1, 1.1, 1.1,
1.1));
vuchar_res = vec_add (vuchar_f,
- ((vector unsigned char)
{'a','a','a','a','a','a','a','a','a','a','a','a','a','a','a','a'}));
+ VDECL16 (vector unsigned char,
'a','a','a','a','a','a','a','a','a','a','a','a','a','a','a','a'));
return vint_res;
}
@@ -90,35 +102,42 @@
int
main (void)
{
- vector int result = {-1,-1,-1,-1};
- vector short x = {1,2,3,4,5,6,7,8};
- vector int y = {12, 22, 32, 42};
- vector int intv_on_stack = {12, 34, 56, 78};
- vector char a = {'v','e','c','t','o','r',' ','o','f','
','c','h','a','r','s','.' };
- vector float b = {5.5, 4.5, 3.75, 2.25};
- vector float c = {1.25, 3.5, 5.5, 7.75};
-
- vector short x_d = {0,0,0,0,0,0,0,0};
- vector int y_d = {0,0,0,0};
- vector int intv_on_stack_d = {0,0,0,0};
- vector char a_d =
{'q','q','q','q','q','q','q','q','q','q','q','q','q','q','q','q'};
- vector float b_d = {5.0, 5.0, 5.0, 5.0};
- vector float c_d = {3.0, 3.0, 3.0, 3.0};
+ vector signed int result = VDECL4 (vector signed int, -1, -1, -1,
-1);
+ vector signed short x = VDECL8 (vector signed short, 1, 2, 3,4, 5,
6, 7, 8);
+ vector signed int y = VDECL4 (vector signed int, 12, 22, 32, 42);
+ vector signed int intv_on_stack = VDECL4 (vector signed int, 12, 34,
56, 78);
+ vector signed char a = VDECL16 (vector signed char,
'v','e','c','t','o','r',' ','o','f',' ','c','h','a','r','s','.' );
+ vector float b = VDECL4 (vector float, 5.5, 4.5, 3.75, 2.25);
+ vector float c = VDECL4 (vector float, 1.25, 3.5, 5.5, 7.75);
+
+ vector signed short x_d = VDECL8 (vector signed short, 0, 0, 0, 0,
0, 0, 0, 0);
+ vector signed int y_d = VDECL4 (vector signed int, 0, 0, 0, 0);
+ vector signed int intv_on_stack_d = VDECL4 (vector signed int, 0, 0,
0, 0);
+ vector signed char a_d = VDECL16 (vector signed char,
'q','q','q','q','q','q','q','q','q','q','q','q','q','q','q','q');
+ vector float b_d = VDECL4 (vector float, 5.0, 5.0, 5.0, 5.0);
+ vector float c_d = VDECL4 (vector float, 3.0, 3.0, 3.0, 3.0);
int var_int = 44;
short var_short = 3;
struct test_vec_struct vect_struct;
- vect_struct.vshort1 = (vector signed short){1, 2, 3, 4, 5, 6, 7, 8};
- vect_struct.vshort2 = (vector signed short){11, 12, 13, 14, 15, 16,
17, 18};
- vect_struct.vshort3 = (vector signed short){21, 22, 23, 24, 25, 26,
27, 28};
- vect_struct.vshort4 = (vector signed short){31, 32, 33, 34, 35, 36,
37, 38};
+#ifdef __APPLE__
+ unsigned long vrsavex = 0xffffffff;
+ __asm__ volatile ("mtspr 256, %0" : : "r" (vrsavex));
+#endif
+ vect_struct.vshort1 = VDECL8 (vector signed short, 1, 2, 3, 4, 5, 6,
7, 8);
+ vect_struct.vshort2 = VDECL8 (vector signed short, 11, 12, 13, 14,
15, 16, 17, 18);
+ vect_struct.vshort3 = VDECL8 (vector signed short, 21, 22, 23, 24,
25, 26, 27, 28);
+ vect_struct.vshort4 = VDECL8 (vector signed short, 31, 32, 33, 34,
35, 36, 37, 38);
+
marker ();
+
#if 0
/* This line is useful for cutting and pasting from the gdb command
line. */
-
vec_func(vshort,vushort,vint,vuint,vchar,vuchar,vfloat,x,y,a,b,c,intv_on
_stack)
+ vec_func
(vshort,vushort,vint,vuint,vchar,vuchar,vfloat,x,y,a,b,c,intv_on_stack)
#endif
+
result = vec_func (vshort, /* goes in v2 */
vushort, /* goes in v3 */
vint, /* goes in v4 */
Index: altivec-abi.exp
===================================================================
RCS file:
/cvs/Darwin/src/live/cygnus/src/gdb/testsuite/gdb.arch/altivec-abi.exp,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- altivec-abi.exp 2002/09/26 20:58:19 1.1.1.2
+++ altivec-abi.exp 2002/10/07 02:04:11 1.2
@@ -32,8 +32,12 @@
set prms_id 0
set bug_id 0
-if ![istarget "powerpc-*altivec"] then {
- verbose "Skipping altivec abi tests."
+if [istarget "powerpc-*altivec"] {
+ set compile_flags { debug additional_flags=-w }
+} elseif [istarget "powerpc-apple-*"] {
+ set compile_flags { debug additional_flags=-w
additional_flags=-faltivec }
+} else {
+ verbose "Skipping altivec register tests."
return
}
@@ -42,7 +46,7 @@
set src1 ${srcdir}/${subdir}/${testfile}.c
-if { [gdb_compile ${src1} ${binfile} executable {debug
additional_flags=-w}] != "" } {
+if { [gdb_compile ${src1} ${binfile} executable ${compile_flags}] !=
"" } {
gdb_suppress_entire_file "Testcase compile failed, so all tests
in this file will automatically fail."
}
@@ -60,7 +64,7 @@
gdb_test "b marker" "Breakpoint 2 at.*file.*altivec-abi.c, line
\[0-9\]+." "break marker"
gdb_test "continue" "Breakpoint 2.*marker.*altivec-abi.c.*" "continue
to marker"
-gdb_test "finish" "Run till exit from .0.*in
marker.*at.*altivec-abi.c.*main \\(\\) at.*altivec-abi.c.*result =
vec_func \\(vshort,.*goes in v2.*" "back to main (1)"
+gdb_test "finish" "Run till exit from
.0.*marker.*at.*altivec-abi.c.*main \\(\\) at.*altivec-abi.c.*result =
vec_func \\(vshort,.*goes in v2.*" "back to main (1)"
# now all the arguments of vec_fun are initialized
Index: altivec-regs.c
===================================================================
RCS file:
/cvs/Darwin/src/live/cygnus/src/gdb/testsuite/gdb.arch/altivec-regs.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- altivec-regs.c 2002/08/11 23:27:05 1.1.1.1
+++ altivec-regs.c 2002/10/07 02:04:11 1.2
@@ -1,4 +1,7 @@
+#ifndef __APPLE__
#include <altivec.h>
+#endif
+
#include <stdio.h>
vector unsigned int
@@ -20,12 +23,18 @@
vector unsigned int z;
int a;
+#ifdef __APPLE__
+ unsigned long vrsavex = 0xffffffff;
+ __asm__ volatile ("mtspr 256, %0" : : "r" (vrsavex));
+#else
/* This line may look unnecessary but we do need it, because we want
to
have a line to do a next over (so that gdb refetches the
registers)
and we don't want the code to change any vector registers.
The splat operations below modify the VRs,i
so we don't want to execute them yet. */
a = 9;
+#endif
+
x = ((vector unsigned int) vec_splat_u8 (-2));
y = ((vector unsigned int) vec_splat_u8 (1));
Index: altivec-regs.exp
===================================================================
RCS file:
/cvs/Darwin/src/live/cygnus/src/gdb/testsuite/gdb.arch/altivec-
regs.exp,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- altivec-regs.exp 2002/08/11 23:27:05 1.1.1.1
+++ altivec-regs.exp 2002/10/07 02:04:11 1.2
@@ -32,7 +32,13 @@
set prms_id 0
set bug_id 0
-if ![istarget "powerpc-*altivec"] then {
+if [istarget "powerpc-*altivec"] {
+ set vrbase "vr"
+ set compile_flags { debug additional_flags=-w }
+} elseif [istarget "powerpc-apple-*"] {
+ set vrbase "v"
+ set compile_flags { debug additional_flags=-w
additional_flags=-faltivec }
+} else {
verbose "Skipping altivec register tests."
return
}
@@ -41,7 +47,7 @@
set binfile ${objdir}/${subdir}/${testfile}
set src1 ${srcdir}/${subdir}/${testfile}.c
-if { [gdb_compile ${src1} ${binfile} executable {debug
additional_flags=-w}] != "" } {
+if { [gdb_compile ${src1} ${binfile} executable ${compile_flags}] !=
"" } {
gdb_suppress_entire_file "Testcase compile failed, so all tests
in this file will automatically fail."
}
@@ -60,7 +66,7 @@
# set all the registers integer portions to 1
for {set i 0} {$i < 32} {incr i 1} {
for {set j 0} {$j < 4} {incr j 1} {
- gdb_test "set \$vr$i.v4_int32\[$j\] = 1" "" "set reg
vr$i.v4si.f\[$j\]"
+ gdb_test "set \$$vrbase$i.v4_int32\[$j\] = 1" "" "set reg
$vrbase$i.v4si.f\[$j\]"
}
}
@@ -88,13 +94,19 @@
# b) the register read (below) also works.
if {$endianness == "big"} {
-set vector_register ".uint128 = 0x00000001000000010000000100000001,
v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
0x1.."
+ set hex_vector ".uint128 = 0x00000001000000010000000100000001,
v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
0x1.."
} else {
-set vector_register ".uint128 = 0x00000001000000010000000100000001,
v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
0x0.."
+ set hex_vector ".uint128 = 0x00000001000000010000000100000001,
v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
0x0.."
+}
+
+if {$endianness == "big"} {
+ set decimal_vector ".uint128 =
0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45,
1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0,
1, 0, 1., v16_int8 = ..0.0.0.001.0.0.0.001.0.0.0.001.0.0.0.001.."
+} else {
+ set decimal_vector ".uint128 =
0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45,
1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1,
0, 1, 0., v16_int8 = ..001.0.0.0.001.0.0.0.001.0.0.0.001.0.0.."
}
for {set i 0} {$i < 32} {incr i 1} {
- gdb_test "info reg vr$i" "vr$i.*$vector_register" "info reg
vr$i"
+ gdb_test "info reg $vrbase$i" "$vrbase$i.*$decimal_vector"
"info reg $vrbase$i"
}
gdb_test "info reg vrsave" "vrsave.*0x1" "info reg vrsave"
@@ -106,22 +118,21 @@
# null char in a string and doesn't print it. This is not a failure,
but
# the way gdb works.
-if {$endianness == "big"} {
- set decimal_vector ".uint128 =
0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45,
1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0,
1, 0, 1., v16_int8 = ..0.0.0.001.0.0.0.001.0.0.0.001.0.0.0.001.."
-} else {
- set decimal_vector ".uint128 =
0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45,
1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1,
0, 1, 0., v16_int8 = ..001.0.0.0.001.0.0.0.001.0.0.0.001.0.0.."
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "print \$$vrbase$i" ".* = $decimal_vector" "print
$vrbase$i (natural)"
}
for {set i 0} {$i < 32} {incr i 1} {
- gdb_test "print \$vr$i" ".* = $decimal_vector" "print vr$i"
+ gdb_test "print /x \$$vrbase$i" ".* = $hex_vector" "print
$vrbase$i (hex)"
}
gdb_test "print \$vrsave" ".* = 1" "print vrsave"
gdb_test "print \$vscr" ".* = 1" "print vscr"
+if 0 {
for {set i 0} {$i < 32} {incr i 1} {
- set pattern$i ".*vr$i.*"
- append pattern$i $vector_register
+ set pattern$i ".*$vrbase$i.*"
+ append pattern$i $decimal_vector
}
send_gdb "info powerpc altivec\n"
@@ -160,6 +171,7 @@
[$pattern31]
"\[ \t\n\r\]+vscr\[ \t\]+0x1"
"\[ \t\n\r\]+vrsave\[ \t\]+0x1"
+}
}
gdb_test "break vector_fun" \
More information about the Gdb-patches
mailing list