[SIM PATCH RFA] add new insn opcode print format, convert some insns

[cgd@broadcom.com]

Asking for approval on this since it touches the generic igen code,
and maybe somebody would rather I do it differently.  8-)

I could have just used %lx, but i'm really kinda allergic to mixing
decimal and hex in numeric printouts without using the leading 0x for
hex.

Testing consisted of verifying that things till compile (which is all
that's really necessary for this), but it'll be in my next full check
run too.  8-)


chris
===================================================================
[ igen/ChangeLog ]
2002-03-05  Chris Demetriou  <cgd@broadcom.com>

	* igen.c (print_itrace_format): Add support for a new "%#lx" format.

[ mips/ChangeLog ]
2002-02-05  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
	immediate or code as a hex value with the "%#lx" format.
	(ANDI): Likewise, and fix printed instruction name.

Index: igen/igen.c
===================================================================
RCS file: /cvs/src/src/sim/igen/igen.c,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 igen.c
--- igen.c	1999/04/16 01:35:04	1.1.1.1
+++ igen.c	2002/03/05 19:24:30
@@ -445,6 +445,17 @@ print_itrace_format (lf *file,
 		      lf_write (file, param, strlen_param);
 		    }
 		}
+	      else if (strncmp (fmt, "%#lx<", 5) == 0)
+		/* simple hex with 0x prefix*/
+		{
+		  if (pass == 1)
+		    lf_printf (file, "%%#lx");
+		  else
+		    {
+		      lf_printf (file, "(unsigned long) ");
+		      lf_write (file, param, strlen_param);
+		    }
+		}
 	      else if (strncmp (fmt, "%08lx<", 6) == 0)
 		/* simple hex */
 		{
Index: mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.32
diff -u -p -r1.32 mips.igen
--- mips.igen	2002/03/05 07:34:01	1.32
+++ mips.igen	2002/03/05 19:24:30
@@ -408,7 +408,7 @@
 
 
 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
-"and r<RT>, r<RS>, <IMMEDIATE>"
+"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII:
@@ -800,7 +800,7 @@
 
 
 000000,20.CODE,001101:SPECIAL:32::BREAK
-"break <CODE>"
+"break %#lx<CODE>"
 *mipsI:
 *mipsII:
 *mipsIII:
@@ -1775,7 +1775,7 @@
 
 
 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
-"lui r<RT>, <IMMEDIATE>"
+"lui r<RT>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII:
@@ -2096,7 +2096,7 @@
 }
 
 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
-"ori r<RT>, r<RS>, <IMMEDIATE>"
+"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII:
@@ -2736,7 +2736,7 @@
 
 
 000000,20.CODE,001100:SPECIAL:32::SYSCALL
-"syscall <CODE>"
+"syscall %#lx<CODE>"
 *mipsI:
 *mipsII:
 *mipsIII:
@@ -2948,7 +2948,7 @@
 }
 
 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
-"xori r<RT>, r<RS>, <IMMEDIATE>"
+"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
 *mipsI:
 *mipsII:
 *mipsIII: