SH5 simulator contribution

[Joern Rennecke]

ac131313@cygnus.com wrote:
> 
> > So I don't see that you gain anything by unifying the numbering scheme
> >> > in the gdb <-> sim interface, as it would be at odds with the interface
> >> > to gcc and the hardware interfaces.
> >
> >>
> >> Formalizing would be a better word.  So that GDB and the SIM can agree
> >> on the register numbers and their sizes without needing to know the
> >> others internals.
> >
> >
> > They only need to know if the program is for an sh5 or an earlier processor.
> > This information is readily available from the elf flags (the lower five bits
> Having just looked at a different target (similar problem), I think
> having a single file that assigns different number ranges to the sh4 vs
> sh64 registers would be best.  That would make it easy to detect things
> like trying to fetch an SH64 register from the SH4 sim.

Using the current raw / pseudo-register distinction, that would lead to funny
artifacts: the sh and sh64 raw registers would all come first, and only then
the can the pseudo registers follow.

In regcache.c:fetch_register / store_register, you added this comment:

   /* NOTE: cagney/2001-12-04: Legacy targets were using fetch/store
     pseudo-register as a way of handling registers that needed to be
     constructed from one or more raw registers.  New targets instead
     use gdbarch register read/write.  */

I suppose I could handle all the pseudos in sim_fetch_register /
sim_store_register,
but then the hardware interfaces would break.

So maybe for the pre-sh5 targets, we should continue to use a relatively low
raw register threshold so that the pseudo registers can immediately follow;
The sh64 simulator can use a higher threshold that makes the sh4 pseudos into
registers that are read/stored with sim_read_register / sim_store_register,
i.e. eventuially via sh64_fetch_register / sh64_store_register.
Then the sh1..sh4 register numbers can be used for the compact registers, too.

	
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