patch: sim/mips/mips.igen: check use of 64-bit insns, fix tracing.
Chris G. Demetriou
cgd@sibyte.com
Wed Dec 6 08:47:00 GMT 2000
The following patch does a few things:
(1) some minor spacing (and one bit of code) cleanup/consistency.
(2) Adds a new function to check whether or not an 64-bit instruction
is actually usable at a given time. (Right now, the function there
always allows it, but that'll change.)
(3) Adds a few input and result tracing calls where they were
previously missing.
(It's an extract from our development tree.)
Anyway, it's been tested with mipstx39-elf and mips64-elf using the
procedure found in:
http://sources.redhat.com/ml/gdb/2000-12/msg00015.html
(and the diff of summary files with those from an unmodified tree is
clean).
Applies over previous patches, in sim/mips.
2000-12-06 Chris Demetriou cgd@sibyte.com
* mips.igen: Adjust comments and spacing.
* mips.igen (check_u64): New function to check whether
a given 64-bit opcode is usable.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU,
DSLL, DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32,
DSRLV, DSUB, DSUBU, LDL, LDR): Use check_u64.
* mips.igen (do_multx): Add some casts to signed64 to
improve tests of values being less than 0.
* mips.igen (do_dsll, DSLL32, do_dsllv, do_dsra, DSRA32,
do_dsrl, DSRL32, do_dsrlv, JAL, JALR): Add input and
result tracing.
chris
===============
diff -rc ../src.P02/sim/mips/mips.igen ./sim/mips/mips.igen
*** ../src.P02/sim/mips/mips.igen Tue Dec 5 16:58:30 2000
--- ./sim/mips/mips.igen Tue Dec 5 19:18:03 2000
***************
*** 234,240 ****
--- 234,254 ----
}
+ // Helper:
+ //
+ // Check that the given 64-bit instruction can currently be used.
+ //
+ :function:::void:check_u64:instruction_word insn
+ *mipsIII:
+ *mipsIV:
+ *vr4100:
+ *vr5000:
+ {
+ // Check that the given 64-bit instruction can currently be used.
+ }
+
+
//
// MIPS Architecture:
//
***************
*** 283,289 ****
}
-
:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
--- 297,302 ----
***************
*** 305,311 ****
}
-
:function:::void:do_addu:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
--- 318,323 ----
***************
*** 327,333 ****
}
-
:function:::void:do_and:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
--- 339,344 ----
***************
*** 770,775 ****
--- 781,787 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
***************
*** 788,793 ****
--- 800,806 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
{
ALU64_BEGIN (GPR[RS]);
***************
*** 798,804 ****
}
-
:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
--- 811,816 ----
***************
*** 813,823 ****
*vr4100:
*vr5000:
{
do_daddiu (SD_, RS, RT, IMMEDIATE);
}
-
:function:::void:do_daddu:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
--- 825,835 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_daddiu (SD_, RS, RT, IMMEDIATE);
}
:function:::void:do_daddu:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
***************
*** 832,842 ****
*vr4100:
*vr5000:
{
do_daddu (SD_, RS, RT, RD);
}
-
:function:::void:do_ddiv:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
--- 844,854 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_daddu (SD_, RS, RT, RD);
}
:function:::void:do_ddiv:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 874,884 ****
*vr4100:
*vr5000:
{
do_ddiv (SD_, RS, RT);
}
-
:function:::void:do_ddivu:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
--- 886,896 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_ddiv (SD_, RS, RT);
}
:function:::void:do_ddivu:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 911,921 ****
*vr4100:
*vr5000:
{
do_ddivu (SD_, RS, RT);
}
-
:function:::void:do_div:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
--- 923,933 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_ddivu (SD_, RS, RT);
}
:function:::void:do_div:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 956,962 ****
}
-
:function:::void:do_divu:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
--- 968,973 ----
***************
*** 969,979 ****
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
! else
! {
! LO = EXTEND32 (n / d);
! HI = EXTEND32 (n % d);
! }
}
TRACE_ALU_RESULT2 (HI, LO);
}
--- 980,990 ----
LO = EXTEND32 (0x80000000);
HI = EXTEND32 (0);
}
! else
! {
! LO = EXTEND32 (n / d);
! HI = EXTEND32 (n % d);
! }
}
TRACE_ALU_RESULT2 (HI, LO);
}
***************
*** 992,998 ****
}
-
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
unsigned64 lo;
--- 1003,1008 ----
***************
*** 1011,1024 ****
sign = 0;
if (signed_p)
{
! if (op1 < 0)
{
! op1 = - op1;
++sign;
}
! if (op2 < 0)
{
! op2 = - op2;
++sign;
}
}
--- 1021,1034 ----
sign = 0;
if (signed_p)
{
! if ((signed64)op1 < 0)
{
! op1 = -op1;
++sign;
}
! if ((signed64)op2 < 0)
{
! op2 = -op2;
++sign;
}
}
***************
*** 1064,1069 ****
--- 1074,1080 ----
*mipsIV:
*vr4100:
{
+ check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, 0);
}
***************
*** 1072,1077 ****
--- 1083,1089 ----
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, RD);
}
***************
*** 1088,1093 ****
--- 1100,1106 ----
*mipsIV:
*vr4100:
{
+ check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, 0);
}
***************
*** 1096,1116 ****
"dmultu r<RS>, r<RT>"
*vr5000:
{
do_dmultu (SD_, RS, RT, RD);
}
:function:::void:do_dsll:int rt, int rd, int shift
{
GPR[rd] = GPR[rt] << shift;
}
- :function:::void:do_dsllv:int rs, int rt, int rd
- {
- int s = MASKED64 (GPR[rs], 5, 0);
- GPR[rd] = GPR[rt] << s;
- }
-
-
000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
--- 1109,1125 ----
"dmultu r<RS>, r<RT>"
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, RD);
}
:function:::void:do_dsll:int rt, int rd, int shift
{
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = GPR[rt] << shift;
+ TRACE_ALU_RESULT (GPR[rd]);
}
000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
***************
*** 1118,1123 ****
--- 1127,1133 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsll (SD_, RT, RD, SHIFT);
}
***************
*** 1130,1138 ****
--- 1140,1160 ----
*vr5000:
{
int s = 32 + SHIFT;
+ check_u64 (SD_, instruction_0);
+ TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = GPR[RT] << s;
+ TRACE_ALU_RESULT (GPR[RD]);
}
+
+ :function:::void:do_dsllv:int rs, int rt, int rd
+ {
+ int s = MASKED64 (GPR[rs], 5, 0);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = GPR[rt] << s;
+ TRACE_ALU_RESULT (GPR[rd]);
+ }
+
000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
***************
*** 1140,1154 ****
*vr4100:
*vr5000:
{
do_dsllv (SD_, RS, RT, RD);
}
:function:::void:do_dsra:int rt, int rd, int shift
{
! GPR[rd] = ((signed64) GPR[rt]) >> shift;
}
-
000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
--- 1162,1179 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsllv (SD_, RS, RT, RD);
}
+
:function:::void:do_dsra:int rt, int rd, int shift
{
! TRACE_ALU_INPUT2 (GPR[rt], shift);
! GPR[rd] = ((signed64) GPR[rt]) >> shift; /* Assumes sign extension. */
! TRACE_ALU_RESULT (GPR[rd]);
}
000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
***************
*** 1156,1161 ****
--- 1181,1187 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsra (SD_, RT, RD, SHIFT);
}
***************
*** 1168,1174 ****
*vr5000:
{
int s = 32 + SHIFT;
! GPR[RD] = ((signed64) GPR[RT]) >> s;
}
--- 1194,1203 ----
*vr5000:
{
int s = 32 + SHIFT;
! check_u64 (SD_, instruction_0);
! TRACE_ALU_INPUT2 (GPR[RT], s);
! GPR[RD] = ((signed64) GPR[RT]) >> s; /* Assumes sign extension. */
! TRACE_ALU_RESULT (GPR[RD]);
}
***************
*** 1176,1182 ****
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
! GPR[rd] = ((signed64) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
--- 1205,1211 ----
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
! GPR[rd] = ((signed64) GPR[rt]) >> s; /* Assumes sign extension. */
TRACE_ALU_RESULT (GPR[rd]);
}
***************
*** 1187,1201 ****
*vr4100:
*vr5000:
{
do_dsrav (SD_, RS, RT, RD);
}
:function:::void:do_dsrl:int rt, int rd, int shift
{
GPR[rd] = (unsigned64) GPR[rt] >> shift;
}
-
000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
--- 1216,1233 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsrav (SD_, RS, RT, RD);
}
+
:function:::void:do_dsrl:int rt, int rd, int shift
{
+ TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = (unsigned64) GPR[rt] >> shift;
+ TRACE_ALU_RESULT (GPR[rd]);
}
000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
***************
*** 1203,1208 ****
--- 1235,1241 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsrl (SD_, RT, RD, SHIFT);
}
***************
*** 1215,1221 ****
--- 1248,1257 ----
*vr5000:
{
int s = 32 + SHIFT;
+ check_u64 (SD_, instruction_0);
+ TRACE_ALU_INPUT2 (GPR[RT], s);
GPR[RD] = (unsigned64) GPR[RT] >> s;
+ TRACE_ALU_RESULT (GPR[RD]);
}
***************
*** 1222,1232 ****
:function:::void:do_dsrlv:int rs, int rt, int rd
{
int s = MASKED64 (GPR[rs], 5, 0);
GPR[rd] = (unsigned64) GPR[rt] >> s;
}
-
-
000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
--- 1258,1268 ----
:function:::void:do_dsrlv:int rs, int rt, int rd
{
int s = MASKED64 (GPR[rs], 5, 0);
+ TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = (unsigned64) GPR[rt] >> s;
+ TRACE_ALU_RESULT (GPR[rd]);
}
000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
***************
*** 1234,1239 ****
--- 1270,1276 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsrlv (SD_, RS, RT, RD);
}
***************
*** 1245,1250 ****
--- 1282,1288 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
{
ALU64_BEGIN (GPR[RS]);
***************
*** 1269,1274 ****
--- 1307,1313 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
do_dsubu (SD_, RS, RT, RD);
}
***************
*** 1305,1310 ****
--- 1344,1350 ----
address_word region = (NIA & MASK (63, 28));
GPR[31] = CIA + 8;
DELAY_SLOT (region | (INSTR_INDEX << 2));
+ TRACE_ALU_RESULT (GPR[31]);
}
000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
***************
*** 1321,1326 ****
--- 1361,1367 ----
address_word temp = GPR[RS];
GPR[RD] = CIA + 8;
DELAY_SLOT (temp);
+ TRACE_ALU_RESULT (GPR[RD]);
}
***************
*** 1423,1428 ****
--- 1464,1470 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
***************
*** 1434,1439 ****
--- 1476,1482 ----
*vr4100:
*vr5000:
{
+ check_u64 (SD_, instruction_0);
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
***************
*** 1796,1802 ****
}
-
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI:
--- 1839,1844 ----
***************
*** 1812,1818 ****
}
-
:function:::void:do_mult:int rs, int rt, int rd
{
signed64 prod;
--- 1854,1859 ----
***************
*** 2253,2259 ****
}
-
:function:::void:do_sltu:int rs, int rt, int rd
{
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
--- 2294,2299 ----
***************
*** 2297,2303 ****
}
-
:function:::void:do_srav:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
--- 2337,2342 ----
***************
*** 2321,2327 ****
}
-
:function:::void:do_srl:int rt, int rd, int shift
{
unsigned32 temp = (unsigned32) GPR[rt] >> shift;
--- 2360,2365 ----
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