[binutils-gdb] gdb/riscv: add systemtap support

[Andrew Burgess]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2f79f2e767c167f289d00c02dc43832c0fc2faec

commit 2f79f2e767c167f289d00c02dc43832c0fc2faec
Author: Andrew Burgess <aburgess@redhat.com>
Date:   Sat Mar 18 15:15:49 2023 +0000

    gdb/riscv: add systemtap support
    
    This commit is initial support for SystemTap for RISC-V Linux.  The
    following two tests exercise SystemTap functionality, and are showing
    many failures, which are all fixed by this commit:
    
      gdb.cp/exceptprint.exp
      gdb.base/stap-probe.exp
    
    One thing I wasn't sure about is if the SystemTap support should be
    Linux specific, or architecture specific.  For aarch64, arm, ia64, and
    ppc, the SystemTap support seems to libe in the ARCH-linux-tdep.c
    file, while for amd64, i386, and s390 the implementation lives in
    ARCH-tdep.c.  I have no idea which of these is the better choice -- or
    maybe both choices are correct in the right circumstances, and I'm
    just not aware of how to choose between them.
    
    Anyway, for this patch I selected riscv-tdep.c (though clearly, moving
    the changes to riscv-linux-tdep.c is trivial if anyone thinks that's a
    more appropriate location).
    
    The stap-probe.exp file tests immediate, register, and register
    indirect operands, all of which appear to be working fine with this
    commit.  The generic expression support doesn't appear to be
    architecture specific, so I'd expect that to work fine too.

Diff:
---
 gdb/riscv-tdep.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 388ce8c2519..8024ffed3c2 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -56,6 +56,7 @@
 #include "prologue-value.h"
 #include "arch/riscv.h"
 #include "riscv-ravenscar-thread.h"
+#include "safe-ctype.h"
 
 /* The stack must be 16-byte aligned.  */
 #define SP_ALIGNMENT 16
@@ -3780,6 +3781,33 @@ riscv_gnu_triplet_regexp (struct gdbarch *gdbarch)
   return "riscv(32|64)?";
 }
 
+/* Implementation of `gdbarch_stap_is_single_operand', as defined in
+   gdbarch.h.  */
+
+static int
+riscv_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
+{
+  return (ISDIGIT (*s) /* Literal number.  */
+	  || *s == '(' /* Register indirection.  */
+	  || ISALPHA (*s)); /* Register value.  */
+}
+
+/* String that appears before a register name in a SystemTap register
+   indirect expression.  */
+
+static const char *const stap_register_indirection_prefixes[] =
+{
+  "(", nullptr
+};
+
+/* String that appears after a register name in a SystemTap register
+   indirect expression.  */
+
+static const char *const stap_register_indirection_suffixes[] =
+{
+  ")", nullptr
+};
+
 /* Initialize the current architecture based on INFO.  If possible,
    re-use an architecture from ARCHES, which is a list of
    architectures already created during this debugging session.
@@ -4020,6 +4048,13 @@ riscv_gdbarch_init (struct gdbarch_info info,
 					  disassembler_options_riscv ());
   set_gdbarch_disassembler_options (gdbarch, &riscv_disassembler_options);
 
+  /* SystemTap Support.  */
+  set_gdbarch_stap_is_single_operand (gdbarch, riscv_stap_is_single_operand);
+  set_gdbarch_stap_register_indirection_prefixes
+    (gdbarch, stap_register_indirection_prefixes);
+  set_gdbarch_stap_register_indirection_suffixes
+    (gdbarch, stap_register_indirection_suffixes);
+
   /* Hook in OS ABI-specific overrides, if they have been registered.  */
   gdbarch_init_osabi (info, gdbarch);