[binutils-gdb] sim: testsuite: flatten tree
Michael Frysinger
vapier@sourceware.org
Sat Jan 16 00:19:08 GMT 2021
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=1368b914e93a3af332f787d3d41c106d11bb90da
commit 1368b914e93a3af332f787d3d41c106d11bb90da
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Jan 5 22:09:57 2021 -0500
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diff:
---
sim/testsuite/ChangeLog | 5 +++++
sim/testsuite/Makefile.in | 1 -
sim/testsuite/{sim => }/aarch64/ChangeLog | 0
sim/testsuite/{sim => }/aarch64/adds.s | 0
sim/testsuite/{sim => }/aarch64/addv.s | 0
sim/testsuite/{sim => }/aarch64/allinsn.exp | 0
sim/testsuite/{sim => }/aarch64/bit.s | 0
sim/testsuite/{sim => }/aarch64/cmtst.s | 0
sim/testsuite/{sim => }/aarch64/cnt.s | 0
sim/testsuite/{sim => }/aarch64/fcmXX.s | 0
sim/testsuite/{sim => }/aarch64/fcmp.s | 0
sim/testsuite/{sim => }/aarch64/fcsel.s | 0
sim/testsuite/{sim => }/aarch64/fcvtl.s | 0
sim/testsuite/{sim => }/aarch64/fcvtz.s | 0
sim/testsuite/{sim => }/aarch64/fminnm.s | 0
sim/testsuite/{sim => }/aarch64/fstur.s | 0
sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0
sim/testsuite/{sim => }/aarch64/ldn_single.s | 0
sim/testsuite/{sim => }/aarch64/ldnr.s | 0
sim/testsuite/{sim => }/aarch64/mla.s | 0
sim/testsuite/{sim => }/aarch64/mls.s | 0
sim/testsuite/{sim => }/aarch64/mul.s | 0
sim/testsuite/{sim => }/aarch64/pass.s | 0
sim/testsuite/{sim => }/aarch64/stn_multiple.s | 0
sim/testsuite/{sim => }/aarch64/stn_single.s | 0
sim/testsuite/{sim => }/aarch64/sumov.s | 0
sim/testsuite/{sim => }/aarch64/sumulh.s | 0
sim/testsuite/{sim => }/aarch64/tbnz.s | 0
sim/testsuite/{sim => }/aarch64/testutils.inc | 0
sim/testsuite/{sim => }/aarch64/uzp.s | 0
sim/testsuite/{sim => }/aarch64/xtl.s | 0
sim/testsuite/{sim => }/aarch64/xtn.s | 0
sim/testsuite/{sim => }/arm/ChangeLog | 0
sim/testsuite/{sim => }/arm/adc.cgs | 0
sim/testsuite/{sim => }/arm/add.cgs | 0
sim/testsuite/{sim => }/arm/allinsn.exp | 0
sim/testsuite/{sim => }/arm/and.cgs | 0
sim/testsuite/{sim => }/arm/b.cgs | 0
sim/testsuite/{sim => }/arm/bic.cgs | 0
sim/testsuite/{sim => }/arm/bl.cgs | 0
sim/testsuite/{sim => }/arm/bx.cgs | 0
sim/testsuite/{sim => }/arm/cmn.cgs | 0
sim/testsuite/{sim => }/arm/cmp.cgs | 0
sim/testsuite/{sim => }/arm/eor.cgs | 0
sim/testsuite/{sim => }/arm/hello.ms | 0
sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp | 0
sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0
sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0
sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0
sim/testsuite/{sim => }/arm/ldm.cgs | 0
sim/testsuite/{sim => }/arm/ldr.cgs | 0
sim/testsuite/{sim => }/arm/ldrb.cgs | 0
sim/testsuite/{sim => }/arm/ldrh.cgs | 0
sim/testsuite/{sim => }/arm/ldrsb.cgs | 0
sim/testsuite/{sim => }/arm/ldrsh.cgs | 0
sim/testsuite/{sim => }/arm/misaligned1.ms | 0
sim/testsuite/{sim => }/arm/misaligned2.ms | 0
sim/testsuite/{sim => }/arm/misaligned3.ms | 0
sim/testsuite/{sim => }/arm/misc.exp | 0
sim/testsuite/{sim => }/arm/mla.cgs | 0
sim/testsuite/{sim => }/arm/mov.cgs | 0
sim/testsuite/{sim => }/arm/movw-movt.ms | 0
sim/testsuite/{sim => }/arm/mrs.cgs | 0
sim/testsuite/{sim => }/arm/msr.cgs | 0
sim/testsuite/{sim => }/arm/mul.cgs | 0
sim/testsuite/{sim => }/arm/mvn.cgs | 0
sim/testsuite/{sim => }/arm/orr.cgs | 0
sim/testsuite/{sim => }/arm/rsb.cgs | 0
sim/testsuite/{sim => }/arm/rsc.cgs | 0
sim/testsuite/{sim => }/arm/sbc.cgs | 0
sim/testsuite/{sim => }/arm/smlal.cgs | 0
sim/testsuite/{sim => }/arm/smull.cgs | 0
sim/testsuite/{sim => }/arm/stm.cgs | 0
sim/testsuite/{sim => }/arm/str.cgs | 0
sim/testsuite/{sim => }/arm/strb.cgs | 0
sim/testsuite/{sim => }/arm/strh.cgs | 0
sim/testsuite/{sim => }/arm/sub.cgs | 0
sim/testsuite/{sim => }/arm/swi.cgs | 0
sim/testsuite/{sim => }/arm/swp.cgs | 0
sim/testsuite/{sim => }/arm/swpb.cgs | 0
sim/testsuite/{sim => }/arm/teq.cgs | 0
sim/testsuite/{sim => }/arm/testutils.inc | 0
sim/testsuite/{sim => }/arm/thumb/adc.cgs | 0
sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/add-sp.cgs | 0
sim/testsuite/{sim => }/arm/thumb/add.cgs | 0
sim/testsuite/{sim => }/arm/thumb/addi.cgs | 0
sim/testsuite/{sim => }/arm/thumb/addi8.cgs | 0
sim/testsuite/{sim => }/arm/thumb/allthumb.exp | 0
sim/testsuite/{sim => }/arm/thumb/and.cgs | 0
sim/testsuite/{sim => }/arm/thumb/asr.cgs | 0
sim/testsuite/{sim => }/arm/thumb/b.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bcc.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bcs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/beq.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bge.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bgt.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bhi.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bic.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ble.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bls.cgs | 0
sim/testsuite/{sim => }/arm/thumb/blt.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bmi.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bne.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bpl.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bvc.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bvs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/cmn.cgs | 0
sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/cmp.cgs | 0
sim/testsuite/{sim => }/arm/thumb/eor.cgs | 0
sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs | 0
sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldmia.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldr.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldrb.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldrh.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldsb.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ldsh.cgs | 0
sim/testsuite/{sim => }/arm/thumb/lsl.cgs | 0
sim/testsuite/{sim => }/arm/thumb/lsr.cgs | 0
sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs | 0
sim/testsuite/{sim => }/arm/thumb/mov.cgs | 0
sim/testsuite/{sim => }/arm/thumb/mul.cgs | 0
sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0
sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0
sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0
sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0
sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0
sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0
sim/testsuite/{sim => }/arm/thumb/push.cgs | 0
sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0
sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0
sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0
sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0
sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0
sim/testsuite/{sim => }/arm/thumb/str.cgs | 0
sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0
sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0
sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0
sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0
sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0
sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0
sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0
sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0
sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0
sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0
sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0
sim/testsuite/{sim => }/arm/tst.cgs | 0
sim/testsuite/{sim => }/arm/umlal.cgs | 0
sim/testsuite/{sim => }/arm/umull.cgs | 0
sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0
sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0
sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0
sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0
sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0
sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0
sim/testsuite/{sim => }/arm/xscale/xscale.exp | 0
sim/testsuite/{sim => }/avr/ChangeLog | 0
sim/testsuite/{sim => }/avr/allinsn.exp | 0
sim/testsuite/{sim => }/avr/pass.s | 0
sim/testsuite/{sim => }/avr/testutils.inc | 0
sim/testsuite/{sim => }/bfin/.gitignore | 0
sim/testsuite/{sim => }/bfin/10272_small.s | 0
sim/testsuite/{sim => }/bfin/10436.s | 0
sim/testsuite/{sim => }/bfin/10622.s | 0
sim/testsuite/{sim => }/bfin/10742.s | 0
sim/testsuite/{sim => }/bfin/10799.s | 0
sim/testsuite/{sim => }/bfin/11080.s | 0
sim/testsuite/{sim => }/bfin/7641.s | 0
sim/testsuite/{sim => }/bfin/ChangeLog | 0
sim/testsuite/{sim => }/bfin/PN_generator.s | 0
sim/testsuite/{sim => }/bfin/a0.s | 0
sim/testsuite/{sim => }/bfin/a0shift.S | 0
sim/testsuite/{sim => }/bfin/a1.s | 0
sim/testsuite/{sim => }/bfin/a10.s | 0
sim/testsuite/{sim => }/bfin/a11.S | 0
sim/testsuite/{sim => }/bfin/a12.s | 0
sim/testsuite/{sim => }/bfin/a2.s | 0
sim/testsuite/{sim => }/bfin/a20.S | 0
sim/testsuite/{sim => }/bfin/a21.s | 0
sim/testsuite/{sim => }/bfin/a22.s | 0
sim/testsuite/{sim => }/bfin/a23.s | 0
sim/testsuite/{sim => }/bfin/a24.s | 0
sim/testsuite/{sim => }/bfin/a25.s | 0
sim/testsuite/{sim => }/bfin/a26.s | 0
sim/testsuite/{sim => }/bfin/a3.s | 0
sim/testsuite/{sim => }/bfin/a30.s | 0
sim/testsuite/{sim => }/bfin/a4.s | 0
sim/testsuite/{sim => }/bfin/a5.s | 0
sim/testsuite/{sim => }/bfin/a6.s | 0
sim/testsuite/{sim => }/bfin/a7.s | 0
sim/testsuite/{sim => }/bfin/a8.s | 0
sim/testsuite/{sim => }/bfin/a9.s | 0
sim/testsuite/{sim => }/bfin/abs-2.S | 0
sim/testsuite/{sim => }/bfin/abs-3.S | 0
sim/testsuite/{sim => }/bfin/abs-4.S | 0
sim/testsuite/{sim => }/bfin/abs.S | 0
sim/testsuite/{sim => }/bfin/abs_acc.s | 0
sim/testsuite/{sim => }/bfin/acc-rot.s | 0
sim/testsuite/{sim => }/bfin/acp5_19.s | 0
sim/testsuite/{sim => }/bfin/acp5_4.s | 0
sim/testsuite/{sim => }/bfin/add_imm7.s | 0
sim/testsuite/{sim => }/bfin/add_shift.S | 0
sim/testsuite/{sim => }/bfin/add_sub_acc.s | 0
sim/testsuite/{sim => }/bfin/addsub_flags.S | 0
sim/testsuite/{sim => }/bfin/algnbug1.s | 0
sim/testsuite/{sim => }/bfin/algnbug2.s | 0
sim/testsuite/{sim => }/bfin/allinsn.exp | 0
sim/testsuite/{sim => }/bfin/argc.c | 0
sim/testsuite/{sim => }/bfin/ashift.s | 0
sim/testsuite/{sim => }/bfin/ashift_flags.s | 0
sim/testsuite/{sim => }/bfin/ashift_left.s | 0
sim/testsuite/{sim => }/bfin/b0.S | 0
sim/testsuite/{sim => }/bfin/b1.s | 0
sim/testsuite/{sim => }/bfin/b2.S | 0
sim/testsuite/{sim => }/bfin/brcc.s | 0
sim/testsuite/{sim => }/bfin/brevadd.s | 0
sim/testsuite/{sim => }/bfin/byteop16m.s | 0
sim/testsuite/{sim => }/bfin/byteop16p.s | 0
sim/testsuite/{sim => }/bfin/byteop1p.s | 0
sim/testsuite/{sim => }/bfin/byteop2p.s | 0
sim/testsuite/{sim => }/bfin/byteop3p.s | 0
sim/testsuite/{sim => }/bfin/byteunpack.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_divq.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_divs.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s | 0
sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s | 0
sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s | 0
sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s | 0
sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s | 0
sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_bp1.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_bp2.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_bp3.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_bp4.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s | 0
sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s | 0
sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s | 0
sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0
sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0
sim/testsuite/{sim => }/bfin/c_calla_subr.s | 0
sim/testsuite/{sim => }/bfin/c_cc2dreg.s | 0
sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S | 0
sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s | 0
sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s | 0
sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S | 0
sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S | 0
sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s | 0
sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0
sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0
sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0
sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0
sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0
sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0
sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 0
sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S | 0
sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s | 0
sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s | 0
sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s | 0
sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s | 0
sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s | 0
sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s | 0
sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s | 0
sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s | 0
sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s | 0
sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s | 0
sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s | 0
sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s | 0
sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s | 0
sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s | 0
sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s | 0
sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s | 0
sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s | 0
sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s | 0
sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s | 0
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sim/testsuite/{sim => }/cris/asm/movsm.ms | 0
sim/testsuite/{sim => }/cris/asm/movsmpc.ms | 0
sim/testsuite/{sim => }/cris/asm/movsr.ms | 0
sim/testsuite/{sim => }/cris/asm/movsrpc.ms | 0
sim/testsuite/{sim => }/cris/asm/movssr.ms | 0
sim/testsuite/{sim => }/cris/asm/movucpc.ms | 0
sim/testsuite/{sim => }/cris/asm/movucr.ms | 0
sim/testsuite/{sim => }/cris/asm/movum.ms | 0
sim/testsuite/{sim => }/cris/asm/movumpc.ms | 0
sim/testsuite/{sim => }/cris/asm/movur.ms | 0
sim/testsuite/{sim => }/cris/asm/movurpc.ms | 0
sim/testsuite/{sim => }/cris/asm/mstep.ms | 0
sim/testsuite/{sim => }/cris/asm/msteppc1.ms | 0
sim/testsuite/{sim => }/cris/asm/msteppc2.ms | 0
sim/testsuite/{sim => }/cris/asm/msteppc3.ms | 0
sim/testsuite/{sim => }/cris/asm/mulv10.ms | 0
sim/testsuite/{sim => }/cris/asm/mulv32.ms | 0
sim/testsuite/{sim => }/cris/asm/mulx.ms | 0
sim/testsuite/{sim => }/cris/asm/neg.ms | 0
sim/testsuite/{sim => }/cris/asm/nonvcv32.ms | 0
sim/testsuite/{sim => }/cris/asm/nopv10t.ms | 0
sim/testsuite/{sim => }/cris/asm/nopv32t.ms | 0
sim/testsuite/{sim => }/cris/asm/nopv32t2.ms | 0
sim/testsuite/{sim => }/cris/asm/nopv32t3.ms | 0
sim/testsuite/{sim => }/cris/asm/nopv32t4.ms | 0
sim/testsuite/{sim => }/cris/asm/not.ms | 0
sim/testsuite/{sim => }/cris/asm/op3.ms | 0
sim/testsuite/{sim => }/cris/asm/opterr1.ms | 0
sim/testsuite/{sim => }/cris/asm/opterr2.ms | 0
sim/testsuite/{sim => }/cris/asm/opterr3.ms | 0
sim/testsuite/{sim => }/cris/asm/opterr4.ms | 0
sim/testsuite/{sim => }/cris/asm/opterr5.ms | 0
sim/testsuite/{sim => }/cris/asm/option1.ms | 0
sim/testsuite/{sim => }/cris/asm/option2.ms | 0
sim/testsuite/{sim => }/cris/asm/option3.ms | 0
sim/testsuite/{sim => }/cris/asm/option4.ms | 0
sim/testsuite/{sim => }/cris/asm/orc.ms | 0
sim/testsuite/{sim => }/cris/asm/orm.ms | 0
sim/testsuite/{sim => }/cris/asm/orq.ms | 0
sim/testsuite/{sim => }/cris/asm/orr.ms | 0
sim/testsuite/{sim => }/cris/asm/pcplus.ms | 0
sim/testsuite/{sim => }/cris/asm/pid1.ms | 0
sim/testsuite/{sim => }/cris/asm/raw1.ms | 0
sim/testsuite/{sim => }/cris/asm/raw10.ms | 0
sim/testsuite/{sim => }/cris/asm/raw11.ms | 0
sim/testsuite/{sim => }/cris/asm/raw12.ms | 0
sim/testsuite/{sim => }/cris/asm/raw13.ms | 0
sim/testsuite/{sim => }/cris/asm/raw14.ms | 0
sim/testsuite/{sim => }/cris/asm/raw15.ms | 0
sim/testsuite/{sim => }/cris/asm/raw16.ms | 0
sim/testsuite/{sim => }/cris/asm/raw17.ms | 0
sim/testsuite/{sim => }/cris/asm/raw2.ms | 0
sim/testsuite/{sim => }/cris/asm/raw3.ms | 0
sim/testsuite/{sim => }/cris/asm/raw4.ms | 0
sim/testsuite/{sim => }/cris/asm/raw5.ms | 0
sim/testsuite/{sim => }/cris/asm/raw6.ms | 0
sim/testsuite/{sim => }/cris/asm/raw7.ms | 0
sim/testsuite/{sim => }/cris/asm/raw8.ms | 0
sim/testsuite/{sim => }/cris/asm/raw9.ms | 0
sim/testsuite/{sim => }/cris/asm/ret.ms | 0
sim/testsuite/{sim => }/cris/asm/rfe.ms | 0
sim/testsuite/{sim => }/cris/asm/rfg.ms | 0
sim/testsuite/{sim => }/cris/asm/rfn.ms | 0
sim/testsuite/{sim => }/cris/asm/sbfs.ms | 0
sim/testsuite/{sim => }/cris/asm/scc.ms | 0
sim/testsuite/{sim => }/cris/asm/sfe.ms | 0
sim/testsuite/{sim => }/cris/asm/subc.ms | 0
sim/testsuite/{sim => }/cris/asm/subm.ms | 0
sim/testsuite/{sim => }/cris/asm/subq.ms | 0
sim/testsuite/{sim => }/cris/asm/subqpc.ms | 0
sim/testsuite/{sim => }/cris/asm/subr.ms | 0
sim/testsuite/{sim => }/cris/asm/subxc.ms [...]
[diff truncated at 100000 bytes]
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