src/sim/testsuite/sim/bfin ChangeLog se_all32b ...

[vapier@sourceware.org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	vapier@sourceware.org	2013-06-24 01:52:33

Modified files:
	sim/testsuite/sim/bfin: ChangeLog se_all32bitopcodes.S 

Log message:
	sim: bfin: se_all32bitopcodes: skip debug insns under the sim
	
	Since the sim has a few fake debug insns that the hardware does not, we
	need to check for those before attempting to run them.  Otherwise we'll
	randomly trigger the sim debug asserts/aborts/halts insns.  On the
	hardware, these are proper invalid insns, and the table catches that.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/ChangeLog.diff?cvsroot=src&r1=1.20&r2=1.21
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/se_all32bitopcodes.S.diff?cvsroot=src&r1=1.4&r2=1.5