src/sim/bfin ChangeLog dv-bfin_uart.h

Thu Mar 24 03:16:00 GMT 2011

CVSROOT:	/cvs/src
Module name:	src
Changes by:	vapier@sourceware.org	2011-03-24 03:16:50

Modified files:
	sim/bfin       : ChangeLog dv-bfin_uart.h 

Log message:
	sim: bfin: define more UART LSR bits
	
	We'll need these bits in an upcoming patch, so map out the whole
	LSR MMR now.
	
	Fix up indentation style while we're here.
	
	Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/ChangeLog.diff?cvsroot=src&r1=1.17&r2=1.18
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/bfin/dv-bfin_uart.h.diff?cvsroot=src&r1=1.1&r2=1.2