[committed] i386: Add V2SFmode NEG, ABS and logic insn patterns [PR95046]

[Uros Bizjak]

gcc/ChangeLog:

2020-05-12  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * config/i386/mmx.md (<code>v2sf2): New insn pattern.
    (*mmx_<code>v2sf2): New insn_and_split pattern.
    (*mmx_nabsv2sf2): Ditto.
    (*mmx_andnotv2sf3): New insn pattern.
    (*mmx_<code>v2sf3): Ditto.
    * config/i386/i386.md (absneg_op): New code attribute.
    * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
    (ix86_build_signbit_mask): Ditto.

testsuite/ChangeLog:

2020-05-12  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * gcc.target/i386/pr95046-2.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Uros.
-------------- next part --------------
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d1c0e354162..17883ffd131 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -15091,6 +15091,7 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value)
     case E_V16SFmode:
     case E_V8SFmode:
     case E_V4SFmode:
+    case E_V2SFmode:
     case E_V8DFmode:
     case E_V4DFmode:
     case E_V2DFmode:
@@ -15131,6 +15132,7 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
     case E_V4SImode:
     case E_V8SFmode:
     case E_V4SFmode:
+    case E_V2SFmode:
       vec_mode = mode;
       imode = SImode;
       break;
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8bfc9cb0b71..722eb9b5ec8 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -954,6 +954,9 @@
 ;; Mapping of abs neg operators
 (define_code_iterator absneg [abs neg])
 
+;; Mapping of abs neg operators to logic operation
+(define_code_attr absneg_op [(abs "and") (neg "xor")])
+
 ;; Base name for x87 insn mnemonic.
 (define_code_attr absneg_mnemonic [(abs "fabs") (neg "fchs")])
 
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index a8f603b94f8..0ec80c06d35 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -238,6 +238,40 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+(define_expand "<code>v2sf2"
+  [(set (match_operand:V2SF 0 "register_operand")
+	(absneg:V2SF
+	  (match_operand:V2SF 1 "register_operand")))]
+  "TARGET_MMX_WITH_SSE"
+  "ix86_expand_fp_absneg_operator (<CODE>, V2SFmode, operands); DONE;")
+
+(define_insn_and_split "*mmx_<code>v2sf2"
+  [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+	(absneg:V2SF
+	  (match_operand:V2SF 1 "register_operand" "%0,x")))
+   (use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
+  "TARGET_MMX_WITH_SSE"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(<absneg_op>:V2SF (match_dup 1) (match_dup 2)))]
+  ""
+  [(set_attr "isa" "noavx,avx")])
+
+(define_insn_and_split "*mmx_nabsv2sf2"
+  [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+	(neg:V2SF
+	  (abs:V2SF
+	    (match_operand:V2SF 1 "register_operand" "%0,x"))))
+   (use (match_operand:V2SF 2 "nonimmediate_operand" "x,x"))]
+  "TARGET_MMX_WITH_SSE"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(ior:V2SF (match_dup 1) (match_dup 2)))]
+  ""
+  [(set_attr "isa" "noavx,avx")])
+
 (define_expand "mmx_addv2sf3"
   [(set (match_operand:V2SF 0 "register_operand")
 	(plus:V2SF
@@ -591,6 +625,41 @@
    (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Parallel single-precision floating point logical operations
+;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define_insn "*mmx_andnotv2sf3"
+  [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+	(and:V2SF
+	  (not:V2SF
+	    (match_operand:V2SF 1 "register_operand" "0,x"))
+	  (match_operand:V2SF 2 "register_operand" "x,x")))]
+  "TARGET_MMX_WITH_SSE"
+  "@
+   andps\t{%2, %0|%0, %2}
+   vandps\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "*mmx_<code>v2sf3"
+  [(set (match_operand:V2SF 0 "register_operand" "=x,x")
+	(any_logic:V2SF
+	  (match_operand:V2SF 1 "register_operand" "%0,x")
+	  (match_operand:V2SF 2 "register_operand" "x,x")))]
+  "TARGET_MMX_WITH_SSE"
+  "@
+   <logic>ps\t{%2, %0|%0, %2}
+   v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "V4SF")])
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel single-precision floating point conversion operations
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-2.c b/gcc/testsuite/gcc.target/i386/pr95046-2.c
new file mode 100644
index 00000000000..277cc2d2e58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-2.c
@@ -0,0 +1,35 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -msse2" } */
+
+
+float r[2], a[2];
+
+float fabsf (float);
+
+void
+test_abs (void)
+{
+  for (int i = 0; i < 2; i++)
+    r[i] = fabsf (a[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?andps" } } */
+
+void
+test_neg (void)
+{
+  for (int i = 0; i < 2; i++)
+    r[i] = -a[i];
+}
+
+/* { dg-final { scan-assembler "\tv?xorps" } } */
+
+void
+test_nabs (void)
+{
+  for (int i = 0; i < 2; i++)
+    r[i] = -fabsf (a[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?orps" } } */