RX: Fixing latency timings for BSET and BLCR insns

[Nick Clifton]

Hi Guys,

  I am applying the attached patch to fix a typo in the timings of the
  BSET and BCLR instructions for the RX port.

Cheers
  Nick

gcc/ChangeLog
2011-03-10  Nick Clifton  <nickc@redhat.com>

	* config/rx/rx.md (bitset_in_memory, bitclr_in_memory: Fix timings.

Index: gcc/config/rx/rx.md
===================================================================
--- gcc/config/rx/rx.md	(revision 170842)
+++ gcc/config/rx/rx.md	(working copy)
@@ -1643,7 +1643,7 @@
   ""
   "bset\t%1, %0.B"
   [(set_attr "length" "3")
-   (set_attr "timings" "34")]
+   (set_attr "timings" "33")]
 )
 
 (define_insn "*bitinvert"
@@ -1689,7 +1689,7 @@
   ""
   "bclr\t%1, %0.B"
   [(set_attr "length" "3")
-   (set_attr "timings" "34")]
+   (set_attr "timings" "33")]
 )
 
 (define_insn "*insv_imm"