ppc 64-bit bridge instructions

Richard Henderson rth@cygnus.com
Thu May 6 15:32:00 GMT 1999


Cort raised the issue of "64-bit bridge" instructions 
(whatever that is -- from context, 32-bit only insns
that are still valid in 64-bit mode for compatibility).

His proposed patch simply moved the affected insns
out of "COM32" and "PPC32" to "COM" and "PPC".  I'd
thought that it would be better to continue marking
them in some way, but the categorization that happens
in the assembler makes this not quite straightforward.

Appended is my proposed patch.  Can anyone think of
a cleaner way this could be done?


r~


	* include/opcode/ppc.h (PPC_OPCODE_64_BRIDGE): New.

	* opcodes/ppc-opc.c (PPC32B, COM32B): New categories.
	(mtsr, mfsr, mtsrin, mfsrin): Use them.

	* gas/config/tc-ppc.c (md_parse_option): Recognize -mppc64bridge.
	(md_begin): Allow bridge insns for ppc64.

Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/binutils/binutils/include/opcode/ppc.h,v
retrieving revision 1.1.1.1
diff -c -p -d -r1.1.1.1 ppc.h
*** ppc.h	1999/05/03 07:29:05	1.1.1.1
--- ppc.h	1999/05/06 22:23:50
*************** extern const int powerpc_num_opcodes;
*** 85,90 ****
--- 85,93 ----
     for the assembler's -many option, and it eliminates duplicates).  */
  #define PPC_OPCODE_ANY (0200)
  
+ /* Opcode is supported as part of the 64-bit bridge.  */
+ #define PPC_OPCODE_64_BRIDGE (0400)
+ 
  /* A macro to extract the major opcode from an instruction.  */
  #define PPC_OP(i) (((i) >> 26) & 0x3f)
  
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/binutils/binutils/gas/config/tc-ppc.c,v
retrieving revision 1.1.1.1
diff -c -p -d -r1.1.1.1 tc-ppc.c
*** tc-ppc.c	1999/05/03 07:28:43	1.1.1.1
--- tc-ppc.c	1999/05/06 22:23:50
*************** md_parse_option (c, arg)
*** 766,771 ****
--- 766,776 ----
  	  ppc_cpu = PPC_OPCODE_PPC;
  	  ppc_size = PPC_OPCODE_64;
  	}
+       else if (strcmp (arg, "ppc64bridge") == 0)
+ 	{
+ 	  ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE;
+ 	  ppc_size = PPC_OPCODE_64;
+ 	}
        /* -mcom means assemble for the common intersection between Power
  	 and PowerPC.  At present, we just allow the union, rather
  	 than the intersection.  */
*************** PowerPC options:\n\
*** 872,877 ****
--- 877,883 ----
  -mppc, -mppc32, -m403, -m603, -m604\n\
  			generate code for Motorola PowerPC 603/604\n\
  -mppc64, -m620		generate code for Motorola PowerPC 620\n\
+ -mppc64bridge		generate code for PowerPC 64, including bridge insns\n\
  -mcom			generate code Power/PowerPC common instructions\n\
  -many			generate code for any architecture (PWR/PWRX/PPC)\n\
  -mregnames		Allow symbolic names for registers\n\
*************** md_begin ()
*** 972,978 ****
  
        if ((op->flags & ppc_cpu) != 0
  	  && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
! 	      || (op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == ppc_size))
  	{
  	  const char *retval;
  
--- 978,986 ----
  
        if ((op->flags & ppc_cpu) != 0
  	  && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
! 	      || (op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == ppc_size
! 	      || (ppc_size == PPC_OPCODE_64
! 		  && (op->flags & PPC_OPCODE_64_BRIDGE & ppc_cpu) != 0)))
  	{
  	  const char *retval;
  
Index: gas/opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/binutils/binutils/opcodes/ppc-opc.c,v
retrieving revision 1.1.1.1
diff -c -p -d -r1.1.1.1 ppc-opc.c
*** ppc-opc.c	1999/05/03 07:28:59	1.1.1.1
--- ppc-opc.c	1999/05/06 22:23:50
*************** extract_tbr (insn, invalid)
*** 1267,1273 ****
  #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
  #define PPCCOM	PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
  #define PPC32   PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
! #define PPC64   PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
  #define PPCONLY	PPC_OPCODE_PPC
  #define PPC403	PPC
  #define PPC750	PPC
--- 1267,1274 ----
  #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
  #define PPCCOM	PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
  #define PPC32   PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
! #define PPC32B  PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY | PPC_OPCODE_64_BRIDGE
! #define PPC64   PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY | PPC_OPCODE_64_BRIDGE
  #define PPCONLY	PPC_OPCODE_PPC
  #define PPC403	PPC
  #define PPC750	PPC
*************** extract_tbr (insn, invalid)
*** 1278,1283 ****
--- 1279,1285 ----
  #define	POWER32	PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
  #define	COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
  #define	COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
+ #define	COM32B	PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32 | PPC_OPCODE_64_BRIDGE
  #define	M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
  #define PWRCOM	PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
  #define	MFDEC1	PPC_OPCODE_POWER
*************** const struct powerpc_opcode powerpc_opco
*** 2249,2255 ****
  { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
  { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
  
! { "mtsr",    X(31,210),	XRB_MASK|(1<<20), COM32,	{ SR, RS } },
  
  { "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA, RB } },
  
--- 2251,2257 ----
  { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
  { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
  
! { "mtsr",    X(31,210),	XRB_MASK|(1<<20), COM32B,	{ SR, RS } },
  
  { "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA, RB } },
  
*************** const struct powerpc_opcode powerpc_opco
*** 2293,2299 ****
  { "mullwo.", XO(31,235,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
  { "mulso.",  XO(31,235,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
  
! { "mtsrin",  X(31,242),	XRA_MASK,	PPC32,		{ RS, RB } },
  { "mtsri",   X(31,242),	XRA_MASK,	POWER32,	{ RS, RB } },
  
  { "dcbtst",  X(31,246),	XRT_MASK,	PPC,		{ RA, RB } },
--- 2295,2301 ----
  { "mullwo.", XO(31,235,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
  { "mulso.",  XO(31,235,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
  
! { "mtsrin",  X(31,242),	XRA_MASK,	PPC32B,		{ RS, RB } },
  { "mtsri",   X(31,242),	XRA_MASK,	POWER32,	{ RS, RB } },
  
  { "dcbtst",  X(31,246),	XRT_MASK,	PPC,		{ RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2739,2745 ****
  
  { "lfsux",   X(31,567),	X_MASK,		COM,		{ FRT, RAS, RB } },
  
! { "mfsr",    X(31,595),	XRB_MASK|(1<<20), COM32,	{ RT, SR } },
  
  { "lswi",    X(31,597),	X_MASK,		PPCCOM,		{ RT, RA, NB } },
  { "lsi",     X(31,597),	X_MASK,		PWRCOM,		{ RT, RA, NB } },
--- 2741,2747 ----
  
  { "lfsux",   X(31,567),	X_MASK,		COM,		{ FRT, RAS, RB } },
  
! { "mfsr",    X(31,595),	XRB_MASK|(1<<20), COM32B,	{ RT, SR } },
  
  { "lswi",    X(31,597),	X_MASK,		PPCCOM,		{ RT, RA, NB } },
  { "lsi",     X(31,597),	X_MASK,		PWRCOM,		{ RT, RA, NB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2755,2761 ****
  
  { "lfdux",   X(31,631), X_MASK,		COM,		{ FRT, RAS, RB } },
  
! { "mfsrin",  X(31,659), XRA_MASK,	PPC32,		{ RT, RB } },
  
  { "stswx",   X(31,661), X_MASK,		PPCCOM,		{ RS, RA, RB } },
  { "stsx",    X(31,661), X_MASK,		PWRCOM,		{ RS, RA, RB } },
--- 2757,2763 ----
  
  { "lfdux",   X(31,631), X_MASK,		COM,		{ FRT, RAS, RB } },
  
! { "mfsrin",  X(31,659), XRA_MASK,	PPC32B,		{ RT, RB } },
  
  { "stswx",   X(31,661), X_MASK,		PPCCOM,		{ RS, RA, RB } },
  { "stsx",    X(31,661), X_MASK,		PWRCOM,		{ RS, RA, RB } },


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