RISC-V disassembler

[Ulrich Drepper]

On 9/9/19 11:25 PM, Jim Wilson wrote:
> There is a testfile45.expect.bz2 that doesn't look like it is supposed
> to be part of the patch set.  You probably don't want to commit that one.

Yes, I do.  The x86-64 disassembler had a tiny whitespace bug exposed
through the code.


> There is a testcase for riscv64 but not for riscv32, though the code
> does look like it correctly handles rv32 versus rv64 decodes.  A
> testcase for rv32 would be a nice improvement.

Well, if someone has the time.


> Otherwise, it looks pretty good at a first glance, and I'm not planning
> to do a full review.  Seems to handle the obvious tricky cases
> correctly.  It doesn't support rv128

This necessitates the introduction of ELFCLASS128 first.


> or the q (quadfloat) extension,

Yes, it does.


> We have binutils patches for the draft V
> (vector) and B (bit manipulation) extensions in branches in the
> github.com riscv repos, but these are still changing instruction
> mnemonics and encodings, so not ready for official trees yet.

Which is why I didn't add any of that.

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