RISC-V disassembler

Jim Wilson jimw@sifive.com
Mon Sep 9 21:25:00 GMT 2019

On 9/7/19 2:18 AM, Ulrich Drepper wrote:
> I'll check in the attached patch which implements a disassembler for
> RISC-V.  It also fixes a problem in the x86 disassember, exposed through
> the additions needed for RISC-V.
> Since aside rth, who added the BPF disassembler, no one beside me ever
> worked on that code I will push the changes as soon as I can.

There are some binary bz2 files missing at the end of the patch, but if 
you are committing this yourself that is probably OK.

There is a testfile45.expect.bz2 that doesn't look like it is supposed 
to be part of the patch set.  You probably don't want to commit that one.

There is a testcase for riscv64 but not for riscv32, though the code 
does look like it correctly handles rv32 versus rv64 decodes.  A 
testcase for rv32 would be a nice improvement.

Otherwise, it looks pretty good at a first glance, and I'm not planning 
to do a full review.  Seems to handle the obvious tricky cases 
correctly.  It doesn't support rv128 or the q (quadfloat) extension, but 
then I don't know of anyone using them, and binutils probably doesn't 
handle them correctly either.  We have binutils patches for the draft V 
(vector) and B (bit manipulation) extensions in branches in the 
github.com riscv repos, but these are still changing instruction 
mnemonics and encodings, so not ready for official trees yet.  We just 
need to remember that we have another disassembler to update when the V 
and/or B extensions are finalized.  There are also new CSR registers 
being added regularly, for extensions, and for hardware features like 
the draft CLIC interrupt controller spec, so that is another thing that 
will need occasional updates.


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