[Bug 1001275] Cortex-M (armV7) architecture endian instructions / Applied on lwIP
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Tue Aug 23 20:15:00 GMT 2011
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--- Comment #24 from Ilija Kocho <ilijak@siva.com.mk> 2011-08-23 21:14:19 BST ---
(In reply to comment #23)
> (In reply to comment #19)
> Regarding attachment 1348 [details]
>
> hal_cortexm.cdl (CYGIMP_HAL_ARCH_ENDIAN): reformatted according CDL
> coding style, fixed a typo in description (s/bute/byte) and I would
> have said
>
> + default_value 1
> + description "
> + Cortex-M architecture implements instructions for endian
> + manipulation (byte swapping). If enabled, this feature
> + can produce shorter and faster code for that."
OK. Thanks.
>
> cortexm_regs.h:
>
> Ilija, I missed that you have used such an order for arguments in REV
> macros, for example
>
> +// Reverse word
> +#define CYGARC_REV(_swapped_,_original_) \
> + __asm__ volatile ("rev %0, %1\n" : "=r"(_swapped_) : "r"(_original_))
> +
>
> It looks clear for ARM assembler gurus (dst <- src), and for C-guys it
> looks a bit puzzled, (IMO) they are accustomed to same
I would insist to keep present order. Here are some arguments:
These macros shall be used mainly by people who are familiar with assembler and
they would be surprised if order is not as in assembler.
Also there is a long tradition the destination to be first argument in C
functions. The origins date back to big-bang, look for rationale in K&R book.
Examples strcpy(), strcat(), memcpy()...
> #define HAL_READ_UINT32( _register_, _value_ ) \
What about HAL_WRITE_UINT32(__register__, value)?
>
> Still, I would use prototypes where result returns in the second
> argument. And if you have no objections I would use multiline variants
> for those macros.
>
> #define CYGARC_REV( _origin_, _swapped_ ) \
> asm volatile( "rev %0, %1\n" \
> : "=r" (_swapped_) \
> : "r" (_origin_) \
> );
I wouldn't object, only I don't see the need for it. Present layout doesn't
stretch out of limits. As far as I have seen other architectures (coldfire,
ppc) use same layout.
Ilija
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