xscale icache disable

[Mark Salter]

>>>>> Jani Monoses writes:

>> >              \
>> > -        "mcr    p15,0,r1,c7,c5,0;"  /* invalidate instruction cache
>> > */  \+         /* cpuwait */                                        
>> >          \
>> > +        "mrc    p15,0,r1,c2,c0,0;"  /* arbitrary read   */         
>> >     \
>> > +        "mov    r1,r1;"                                            
>> >     \
>> > +        "sub    pc,pc,#4;"                                         
>> >     \
>> >          "nop;" /* next few instructions may be via cache */        
>> >              \
>> >          "nop;"                                                     
>> >              \
>> >          "nop;"                                                     
>> >              \
>> 
>> Odd. The cache command works fine on the XScale boards I have here.
>> The cores/caches are all the same. Anyway, I have no problem with
>> adding the cpwait. But why did you remove the invalidate instruction?

> yes that was a mistake. I am looking at this again since with these
> changes too it resets now.So could you hold on with applying until I see
> what it is.Especially since it works on your xscale it might be
> something else wrong here.

Could be a bus controller setup problem? Burst access vs non-burst access.
This was the source of trouble for me once.

--Mark