[ECOS]Redboot for FSL TWRK70F120M with Linux kernel booting

Linh Nguyễn nvl1109@gmail.com
Wed Mar 14 08:08:00 GMT 2012


On Wed, Mar 14, 2012 at 2:44 PM, Ilija Kocho <ilijak@siva.com.mk> wrote:
> Hi Linh
>
>
>
> On 14.03.2012 05:39, Linh Nguyễn wrote:
>> Hi all,
>>
>> Does anyone successful porting Redboot for TWRK70F120M hardware board?
>> I have edited HAL of TWRK60N512 to use as TWRK70F120M. It can run but
>> I don't now how to add SDRAM of K70 into linker file and use it.
>> Attached files are linker file that I edited to use SDRAM, I have
>> initialized PLL0 and PLL1 then DDR registers. I can access SDRAM by
>> hard address (like 0x70001000). But when I load a binary file into
>> SDRAM, it shown the warrning as bellow:
>> <code>
>> RedBoot> load -r -v -h 10.207.215.87 -m tftp -b 0x70008000 Image
>> Specified address (0x70008000) is not believed to be in RAM - continue (y/n)? y
>> </code>
>>
>> If you have any ideas about the problems, please let me know :).
>
> You need to report this memory to RedBoot. Look for
> cyg_plf_memory_segment() in twr_k60n512_misc.c (or whatever name you
> have given to this file).
I have done this before. (twr_k70f120m_misc.c attached.)

Can you take a look at the file and show me my mistake :). Or please
share me your linker config & memory segment () that you configure for
DRAM.
>
>> If anyone have ported Redboot to K70 or successful in using SDRAM
>> please share me :).
> Thank you for your offer.
> I am working on K70 port, everything essential seem to work (including
> FPU) but I have problem initializing PLL1. I have read the errata but it
> still doesn't work for me. Is there any trick?
>
> Also when trying to initialize DDR registers the chip freezes, I guess
> that it is because PLL1 is not working but maybe I need to enable
> something else than DDRAM clock.
> Can you send me the clock and DDR initialization sequence you are using?

About clock and DDRAM initialization I follow Kinetis 120MHz bare
metal sample code from Freescale site
(https://www.freescale.com/webapp/Download?colCode=KINETIS_120MHZ_SC&prodCode=K70_120&appType=license&location=null&fpsp=1&Parent_nodeId=1326817898002720905982&Parent_pageType=product&Parent_nodeId=1326817898002720905982&Parent_pageType=product).

kinetis_clocking.c attached contains my PLL0 & PLL1 initialization
sequences. My source code is hard-code for K70 only, so it can't build
for another board. You can find MK70F12.h in the package with link
above.

>
> Regards
>
> Ilija
>

Thanks & Regards,
Linh Nguyen.
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