[ECOS] Re: STM32F4 timers test problem

Morris, Richard Richard.Morris@lifetech.com
Thu Aug 23 22:00:00 GMT 2012


An additional update on the APB timer initialization.

I'm not yet familiar with the process for having code submitted to the source tree, and so I am posting this here.

Upon further reading of the initialization code for the STM32Fx, I found what appears to be a reasonable location for the initialization.

As a result, I moved the APB timer initialization to a place that looks more appropriate in stm32x0g_eval_misc.c.  Right at the beginning of the APB initialization.  (See my previous posts for details leading up to this point.)

__externC void hal_system_init( void )
{
    CYG_ADDRESS base;
    
    // Enable peripheral clocks in RCC

    base = CYGHWR_HAL_STM32_RCC;

    // Enable clocks for timers
    {
      unsigned int reg;
      HAL_READ_UINT32((base + CYGHWR_HAL_STM32_RCC_APB1ENR), reg );
      HAL_WRITE_UINT32((base + CYGHWR_HAL_STM32_RCC_APB1ENR),
		       (reg
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7)
#if (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM12)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM13)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB1ENR_TIM14)
#endif
			)
		       );
      HAL_READ_UINT32((base + CYGHWR_HAL_STM32_RCC_APB2ENR), reg );
      HAL_WRITE_UINT32((base + CYGHWR_HAL_STM32_RCC_APB2ENR),
		       (reg
			| BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8)
#if (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_TIM9)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_TIM10)
			| BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_TIM11)
#endif
			)
		       );
    }

    // All GPIO ports
    // FIXME: this should be done in variant HAL at point of gpio_set
    HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR,
#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) // enable CCM clock
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) |
#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH) |
                     BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI) );




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