[ECOS] gcc miscompiles HAL_DISABLE_INTERRUPTS on Cortex-M3

[Stanislav Meduna]

On 16.02.2011 15:21, Christophe Coutand wrote:

> What happens if you change the macro to this:
> 
> # define HAL_DISABLE_INTERRUPTS(__old)          \
>     __asm__ volatile (                          \
>         "mrs    %0, basepri             \n"     \
>         "mov    r1,%1                   \n"     \
>         "msr    basepri,r1              \n"     \
>         : "=r" (__old)                          \
>         :  "I" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\
>         : "r1"                                  \
>         );
> 
> I usually use I (Immediate value) but I am not so use to ARM processor.

Yup. Either this or
  "=&r" (__old)
(earlyclobber - clobbering before using all inputs) work.

Thanks, I am going to submit the bugreport.

-- 
                                         Stano

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