[ECOS] Timing differences before / after starting scheduler

[Tim Jaacks]

> Are these times the worst case, or the normal case? Has only the worst
> case changed? 
>
> What are other threads doing? Could maybe one of the other threads set
> off a DMA? DMA will compete for the memory bus with the fetch from ROM
> for the executable code, reads from the FIFO and writes to RAM. Hence
> everything will go slower if there is a DMA in action somewhere.
>
> Having said this, your architecture does not sound very robust. Don't
> you have any hardware flow control? Carn't you tell the sender to
> pause while you catch up?
>
>       Andrew
>   
These times are the normal case, and this normal case changed.

There are no other threads present (at least none I created). There is 
only this one thread that uses the according driver. There is no DMA 
activity present in the system as well.

The data comes in with 36MBit/s and there is no possibility of pausing 
the transfer.

Any more ideas? You say, this behaviour should not be normal, eh?

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