[ECOS] ARM926ej Cache and MMU Supprt

Jerin Jacob Jerin.Jacob@maxim-ic.com
Wed Apr 21 20:28:00 GMT 2010

Hi All,

We are in the process of porting eCos on arm926ej based SoC.
We have almost completed the HAL porting.
However, When try to enable MMU and D-cache.
We are facing an issue while running kache1 test case.
The kcache1 test case fails when running with D-cache on and I-cache off( undefined instruction
exception).All other modes like D-cache on and I-cache on work as expected.
In fact, All eCos test cases are passing with  D and I cache enable at start-up.

It would be really great, if some throw some lights to this problem.

Few questions 
1)Has any one verified eCos port with arm926ej ?
2)Can we re-use arm9 code exist for  MMU static table creation and Cache operations for arm926j
3) We are using eCos V3.0, Any specific patches is required to bring up cache on arm926ej for eCos ?

 Implementation details:
 1) Followed MMU table creation and Cache operations code from eCos arm9
 2) Changed default eCos arm D-cache size to 16kb from 8kb
 3) Here is the MMU static entries

Thanks in Advance,

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