[ECOS] Zero vector interrupts (SIVEC=0) on MPC8xxx

Danny Sade danny@channelot.com
Tue Sep 1 08:21:00 GMT 2009

Hi All,
Did anyone encounter zero vector interrupt (SIVEC = 0) on the MPC8xxx ?  I recently encountered this kind of interrupts, and according to Freescale support and the documentation this kind of interrupt may occur during normal operation and a service routine for this interrupt must be provided.
The thing is that the current HAL implementation, at the macro hal_intc_decode at variant.inc, decodes this interrupt as a decrementer interrupt.  As a result, whenever this zero vector interrupt is asserted the tick ISR is called.  If the there are only few such interrupts, this is hardly noticed.  But obviously, when there are many such interrupts all the time related services (such as cyg_thread_delay() ) cannot not function the way they should.
I'm not sure what is causing these zero vector interrupts.  I can tell that it is related to the IDMA - whenever I have a lot of IDMA transactions, I see a lot of zero vector interrupts.

Any ideas?



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