[ECOS] XIP some kernel parts

Sergei Gavrikov sergei.gavrikov@gmail.com
Sat Jul 11 16:40:00 GMT 2009

Hi Folks,

Did anybody try to XIP (exucute in a place) in the _different_ places the
parts of eCos kernel itself? I keep in a mind GCC attribute __section__.

May be it is a stupid idea, but, I thought that would help me to reduce
the ISR/DSR latencies on my target. The different places are: 1) fast
CPU SRAM and 2) slow external RAM. It's pity, but, I cannot put whole
eCos kernel into SRAM (16K). Did anybody try the same (to run a kernel
is divided on the chunks (critical/not critical))?

Why I ask about? I can successfully handle the ISRs every 125 uS using
ROM startup, but, I cannot do the same when application is running in
the external RAM (RAM or ROMRAM startup). And I thought about fast and
unused SRAM for the eCos RTC ISR  handler, handler for pending DSRs,
etc. i.e. to wrap some parts of the kernel with some attribute, e.g.

#define __xipsram noinline __attribute__ ((__section__ (".sram")))

If anybody did try it. Which the routines you tweaked?  Thanks in
advance for any critic and comments.



I would glad hear a talk about the "idea" itself, before anybody will
pronounce "FIQ", "VSR" :-) I dislike an assembler.

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