[ECOS] MCF5282 - bits for DACRx registers
Mon Feb 9 18:51:00 GMT 2009
I'm currently backporting our eCos port for the ColdFire MCF5282 (based
on the old coldfire architecture) to the MCF52xx processor HAL (based on
m68k) contributed by eCosCentric.
The archictecture HAL for MCF52xx processors provides quite a lot of
definitions for the MCF5282. Amongst others, bit definitions for the
SDRAM controller's DACR registers where the motivation behind is not
clear to me. For example, the port size bits
(HAL_MCFxxxx_SDRAMC_DACRx_PS_32, ...) are alredy shifted to the
appropriate position within a DACR register where the command and bank
MUX bits (HAL_MCFxxxx_SDRAMC_DACRx_CBM) are not.
Is there a special intention for not shifting the command and bank MUX
bits to their appropriate position? Has these definitions be made for
allowing to redefine HAL_MCFxxxx_SDRAMC_DACRx_CBM_SHIFT for other
ColdFire processors? Is there already productive code out there which
relies on this definition of the command and bank MUX bits?
If not, I would like to change the bit defintions for the command and
bank MUX bits in var_io.h. If there is a reason for not doing so, our
MCF5282 port will live with the definitions already provided for this
bits. We are planning to contribute this port when it is finished and
therefor we would like to minimize the impact of such "global" changes.
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