[ECOS] NPE ethernet not working with Redboot v2.04
Sun Jun 22 17:33:00 GMT 2008
On Fri, 2008-06-20 at 01:00 -0700, Ravi R wrote:
> I see that the AHBQ Mgr registers are being byte swapped before being
> written and are therefore being written wrong. Eg Q base address is
> being written to where the read/write pointers should be in the
> configuration word. This is being done by IX_OSAL_WRITE_LONG() based
> on a flag IX_OSAL_LE_DC_MAPPING.
> I have built Redboot in LE mode, using the Little Endian template, so
> I assume all defines/byte swappings should be correct.
> But obviously something is not right. Am not sure where the proper
> place is to correct/set the defines.
> There does not seem to be any setting in the ecos.ecc file.
> The Xscale is correctly set to LE, the BYTE_SWAP_EN bit is set in the
> EXPB CONTR. Am not sure if the MMU should/also cause the bytes to be
> swapped when writting to the QMgr registers to compensate for the
> IX_OS_WRITE_LONG() byte swap?
LE mode is just plain weird on the IXP4xx family. There are actually
two forms of LE (address coherent and data coherent). A bit in the
page table controls which form of LE is used for a given mapped area.
BE and LE have been thoroughly tested on the IXDP425 and other boards
so all the details of byte-swapping have already been worked out and
just setting CYGHWR_HAL_ARM_BIGENDIAN should be all that needs to be
If at all possible, the initial debugging of RedBoot and the npe support
should be done in BE mode. That is the natural ordering and you won't
have to worry about the byte-swapping mess with LE mode.
In LE mode, the MMU has to provide two views of memory. If your memory
map has changed from the IXDP425, then you may have to change some of
the values in IxOsalOsIxp400.h to match those memory map changes. Also,
there was errata on some early versions of the IXP425 which did not
correctly handle LE mode. But if you're using a new board, I doubt that
is the problem.
> FYI - Regarding the PHY - I stepped through the code pretty carefully
> and it appears to correctly talk to the Phy - e.g it read the type of
> Phy I am using LXT972 from a Phy register via the MII. (The board has
> only one Phy)
All you need to read/write the PHY regs are mdc and mdio signals. That
doesn't mean that txclk/txdata/rxclk/rxdata/etc are correctly connected.
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