[ECOS] How are DSRs scheduled?

Steven Clugston steven.clugston@newcastle.ac.uk
Wed Jun 11 08:51:00 GMT 2008

I've been trying to find a description of how DSRs are scheduled in
Massa and the api manual, but I've not found anything satisfactory that
I understand.

From what I've read, if two different DSRs are posted they get added to
either a linked list or a table depending on which cdl option is

Are these DSRs run on a first-come first-served basis, i.e. the order in
which they were posted?
Or are they run in some relation to the priority of the ISR source which
posted them?

Do they run as a sort of super high priority thread (all DSRs having the
same high priority)?

My reason for asking is that I'm trying to add a hardware queue facility
to an existing serial driver.
There can be interrupts generated form a number of sources, if the rx
queue is half-full, full, or if the line has become idle.
The queue can hold 16 bytes so after 8 bytes you get the half-full
interrupt. If you send exactly 8 bytes then you get the half-full
interrupt then a short time later the line-idle interrupt. All of these
interrupts are have the same priority.

Unless there is something which I have overlooked, what I am observing
appears to be that when the half-full DSR is in the middle of doing a
block transfer then idle interrupt fires and posts its DSR which runs
straight away and it then tries to do a block transfer before the
original half-full DSR has been given a chance to finish. This then
fires an assert in serial.c.

I didn't think that this was supposed to happen. Can this actually
happen, can one DSR be pre-empted by another?

If so, you're not supposed to use mutexes or anything which can block in
a DSR, so is it reasonable to try an use a
Around the block transfer?

One final point, if I was to instead do all of this in a single DSR
routine which somehow deterimines the context, or ISR source from which
is was called, then would prevent this problem?


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