[ECOS] Init sequence for enabling MMU at mpc5xx fails

[Andrey Baboshin]

Hi, all.

I find following problem.
I enable the MMU in eCos and it executes next code

        # Initialize MMU.
        bl      hal_MMU_init

        # Enable MMU (if desired) so we can safely enable caches.
        lwi     r3,CYG_MSR              # interrupts enabled later
        sync
        mtmsr   r3 (*)
        sync

        # Enable caches
        bl      hal_enable_caches

I have found it fails after (*).
In additional
CYG_MSR = (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS)
CYG_MSR_COMMON = (MSR_FP | MSR_ME | MSR_RI)
IP_BIT = 0
IR_DR_BITS = (MSR_IR | MSR_DR)

Do have anyone some problem?
It works only when I comment mtmsr r3 and followed by it sync.

---
Andrey Baboshin


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