[ECOS] Linker sections & network buffers question.

[Will Wagner]

Hi All,

Have hit a problem where in debug builds the initialisation of the bss 
section to zero takes so long that the chip watchdogs.

I'm using an MPC866 chip and one of the problems with it is that the 
slowest I can set the watchdog to is just over 0.5secs. The bss section 
is just under 3MB and most of that (2MB) are the networking buffers.

So I have a whole load of questions for you:

Do the network buffers really have to reside in the bss section. The 
buffers are just used to create Mempools and looking at the code I don't 
think it relies on the memory being zero'd.

If the buffers don't need to reside in the bss section, anyone know 
which section is the one for variables that don't get set to zero? 
Anyone remind me of the gcc syntax for specifying which section 
something goes in?

On powerpc in vectors.S the sbss & bss sections are zero'd before the 
cache & mmu are enabled which means that the access to the SDRAM will 
not burst (I think) and so be much slower. Any reason for not 
rearranging the code so that cache & mmu are enabled before we try to 
zero sbss & bss?

Thanks,

Will.
-- 
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Will Wagner                                     will_wagner@carallon.com
Senior Project Engineer                  Office Tel: +44 (0)20 7371 2032
Carallon Ltd, Studio G20, Shepherds Building, Rockley Rd, London W14 0DA
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