[ECOS] Wrong asserts in mpc5xx var_intr.h?
Mon Nov 13 10:47:00 GMT 2006
Thanks for your reply!
It works well when the asserts are switched (just as well as with them disabled) and most of the test pass just fine. So i certainly seems the are wrong.
However i get another failed assert when i press ctrl-c from within gdb in the twothreads.c demo:
Thread 1: and now a delay of 224 clock ticks
Thread 0: and now a delay of 243 clock ticks
ASSERT FAIL: <1>hal_misc.chal_default_isr() Spurious Interrupt!!!
[New thread 1]
Program received signal SIGINT, Interrupt.
[Switching to thread 1]
cyg_hal_user_break (regs=0x0) at /home/andfri/Develop/ecos/packages/hal/common/current/src/hal_misc.c:138
Current language: auto; currently c
This doesn't happen when I interrupt for example tests/services/memalloc/common/current/tests/heaptest. Why the difference? I'm not sure that the mpc5xx port has the same problem or if it is one of my modifications to it to make it work on a mpc565 platform that doesn't work. I have no mpc555 hardware to try it on.
Newmad Technologies AB
From: firstname.lastname@example.org [mailto:email@example.com]
Sent: Mon 11/13/2006 9:40 AM
To: Fritiofson, Andreas; firstname.lastname@example.org
Subject: Re: [ECOS] Wrong asserts in mpc5xx var_intr.h?
I wrote this code a long time ago, so I can't say for sure without doing some tests. At first sight, It seems you are right and the Asserts should be the other way around.
I ordered the vectors in such way that all VECTORS < CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1 are from devices that are connected directly to the SIU controller, so they can only have priorities from 0-7. All others >= CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1 come from sources that are connected to the IMB3 controller, so there priorities from 0-31 are valid.
Could you try and see if it solves you problem ?
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