[ECOS] Wrong asserts in mpc5xx var_intr.h?
Mon Nov 13 08:40:00 GMT 2006
I wrote this code a long time ago, so I can't say for sure without doing some tests. At first sight, It seems you are right and the Asserts should be the other way around.
I ordered the vectors in such way that all VECTORS < CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1 are from devices that are connected directly to the SIU controller, so they can only have priorities from 0-7. All others >= CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1 come from sources that are connected to the IMB3 controller, so there priorities from 0-31 are valid.
Could you try and see if it solves you problem ?
>From: Fritiofson, Andreas [mailto:email@example.com]
>Sent: Sunday, November 12, 2006 09:23 AM
>Subject: [ECOS] Wrong asserts in mpc5xx var_intr.h?
>I have made a variant HAL based on mpc5xx and I noticed I always get failed asserts when i build with them enabled. Without asserts enabled it seems to work fine. Upon examination of the code I wonder if the following asserts shouldn't be the other way around?
> if(vector < CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1)
> // Note: highest priority has the lowest numerical value.
> CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
> CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
> CYG_ASSERT( level >= CYGARC_IMB3_PRIORITY_HIGH, "Invalid priority");
> CYG_ASSERT( level <= CYGARC_IMB3_PRIORITY_LOW, "Invalid priority");
>Given the following defines...
>#define CYGARC_SIU_PRIORITY_HIGH 7 // Maximum interrupt priority on SIU
>#define CYGARC_SIU_PRIORITY_LOW 0 // Minimum interrupt prioeirt on SIU
>#define CYGARC_IMB3_PRIORITY_HIGH 31 // Maximum interrupt priority on IMB3
>#define CYGARC_IMB3_PRIORITY_LOW 0 // Minimum interrupt priority on IMB3
>Or is it the defines that should be the other way around, considering the "Note:" above?
>Newmad Technologies AB
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