[ECOS] Thumb support for arm9 variants?
Mon Jun 12 21:39:00 GMT 2006
On Mon, Jun 12, 2006 at 11:12:09PM +0200, Lars Povlsen wrote:
> The offending instructions are indeed inline assembly - its both the
> cache manip and reset:
> cyg_hal_arm9_soft_reset(CYG_ADDRESS entry)
> /* It would probably make more sense to have the
> clear/drain/invalidate after disabling the cache and MMU, but
> then we'd have to know the (unmapped) address of this code. */
> asm volatile ("mrs r1,cpsr;"
> "bic r1,r1,#0x1F;" /* Put processor in SVC mode */
> "orr r1,r1,#0x13;"
> "msr cpsr,r1;"
> "mov r1, #0;"
> "mcr p15,0,r1,c7,c7,0;" /* clear I+DCache */
> "mcr p15,0,r1,c7,c10,4;" /* Drain Write Buffer */
> "mcr p15,0,r1,c8,c7,0;" /* Invalidate TLBs */
> "mrc p15,0,r1,c1,c0,0;"
> "bic r1,r1,#0x1000;" /* disable ICache */
> "bic r1,r1,#0x0007;" /* disable DCache, MMU and
> alignment faults */
> "mcr p15,0,r1,c1,c0,0;"
> "nop;" /* delay 1 */
> "mov pc, %0;" /* delay 2 - next
> instruction should be fetched flat */
> : : "r" (entry) : "r1");
> As this is none of my code (!) - my question is more along the lines as
> why the hal/arm/arm9/* variants does not support thumb - when the arm/*
> variants do? I was under the impression that the former was the most
Most recent, but probably less used in deeply embedded systems than
arm7. Also, arm9 systems tend to be big systems with lots of RAM, so
the more compact thumb is not normally called for.
If you want to use thumb on the arm9 it looks like you are going to
have to do a little work first. Either provide thumb implementation of
this inline assembly, or add mode switch code to change to ARM mode
before and back to thumb afterwards.
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