[ECOS] MPC8xx SMC serial problem

[Will Wagner]

Seem to have fixed my errors, not sure if my error handling is correct.

Here is a diff against current cvs if anyone is interested in merging...

Index: hal/powerpc/quicc/current/include/ppc8xx.h
===================================================================
RCS file: 
/cvs/ecos/ecos/packages/hal/powerpc/quicc/current/include/ppc8xx.h,v
retrieving revision 1.15
diff -w -b -r1.15 ppc8xx.h
970a971,972
 > #define QUICC_BD_CTL_Frame          0x0010  // Framing Error
 > #define QUICC_BD_CTL_Parity         0x0008  // Parity Error
999c1001
< #define QUICC_SMCMR_CLEN(n)   ((n+1)<<11)   // Character length
---
 > #define QUICC_SMCMR_CLEN(n)   (n<<11)       // Character length + 
parity + stop bits
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
===================================================================
RCS file: 
/cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.18
diff -w -b -r1.18 quicc_smc_serial.c
348c348
<     _lcr = smc_select_word_length[new_config->word_length - 
CYGNUM_SERIAL_WORD_LENGTH_5] |
---
 >     _lcr = QUICC_SMCMR_CLEN(new_config->word_length + 
((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + 
((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
976a977
 >                 if((rxbd->ctrl & (QUICC_BD_CTL_Frame | 
QUICC_BD_CTL_Parity)) == 0) {
979a981,987
 >                 }
 >                 else
 >                 {
 >                     // is this necessary?
 >                     rxbd->ctrl &= QUICC_BD_CTL_MASK;
 >                     // should we report the error?
 >                 }
1037a1046
 >                 if((rxbd->ctrl & (QUICC_BD_CTL_Frame | 
QUICC_BD_CTL_Parity)) == 0) {
1040a1050,1056
 >                 }
 >                 else
 >                 {
 >                     // is this necessary?
 >                     rxbd->ctrl &= QUICC_BD_CTL_MASK;
 >                     // should we report the error?
 >                 }
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h
===================================================================
RCS file: 
/cvs/ecos/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h,v
retrieving revision 1.7
diff -w -b -r1.7 quicc_smc_serial.h
61,67d60
< static unsigned int smc_select_word_length[] = {
<     QUICC_SMCMR_CLEN(5),  // 5 bits / word (char)
<     QUICC_SMCMR_CLEN(6),
<     QUICC_SMCMR_CLEN(7),
<     QUICC_SMCMR_CLEN(8)
< };
<

-- 
------------------------------------------------------------------------
Will Wagner                                     will_wagner@carallon.com
Senior Project Engineer                        Office Tel: 0207 371 2032
Carallon Ltd, Studio G20, Shepherds Building, Rockley Rd, London W14 0DA
------------------------------------------------------------------------


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