[ECOS] redboot sdram configuration of ixp425
Tom
tom@netlab.cse.yzu.edu.tw
Thu Feb 2 07:31:00 GMT 2006
Hi All
I am trying to put redboot on a customized board with ixp420 processor.
Our redboot works fine with a 32M byte sdram , but works abnoraml when we
change the sdram size to 16M byte .
We use mfill to test if we can access the whole sdram space .
The command
mfill -b 0x1ee50 -l 0x300000 -p 0x5a -1 ( OK )
can be completed , but if we increase the size to 5M , we can't complete it.
mfill -b 0x1ee50 -l 0x500000 -p 0x5a -1 ( can't complete )
The HW is fine , other bootloader and firmware can work on the HW without any
problem .
below is the configuration changed the new sdram :
1. ixp425.h
#define SDRAM_PHYS_BASE 0x00000000
#define SDRAM_BASE 0x00000000
#define SDRAM_UNCACHED_BASE 0x01000000
#define SDRAM_SIZE 0x01000000
#define IXP425_SDRAM_CONFIG_INIT (SDRAM_CONFIG_CAS_3 | SDRAM_CONFIG_2x4Mx16)
where SDRAM_CONFIG_2x4Mx16 is defined as 0x22
2.hal_platform_extras.h
// 16MB SDRAM
.set __base,0x000
.rept 0x010 - 0x000
FL_SECTION_ENTRY __base,0,3,0,0,1,0
.set __base,__base+1
.endr
// 240MB unused
.rept 0x100 - 0x010
.word 0
.set __base,__base+1
.endr
// 16MB SDRAM (alias)
.rept 0x110 - 0x100
FL_SECTION_ENTRY __base,0,3,0,0,1,0
.set __base,__base+1
.endr
// 240MB Unused
.rept 0x200 - 0x110
.word 0
.set __base,__base+1
.endr
// 16MB SDRAM (uncached)
.set __base,0x000
.rept 0x210 - 0x200
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// 240MB SDRAM (uncached)
.set __base,0x210
.rept 0x300 - 0x210
.word 0
.set __base,__base+1
.endr
// 256MB SDRAM (Data Coherant)
.set __base,0x000
.rept 0x400 - 0x300
FL_SECTION_ENTRY __base,0,3,1,0,1,0
.set __base,__base+1
.endr
// 128MB Unused
.set __base,0x400
.rept 0x480 - 0x400
.word 0
.set __base,__base+1
.endr
// 64MB PCI Data
.rept 0x4C0 - 0x480
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// 64MB Unused
.rept 0x500 - 0x4C0
.word 0
.set __base,__base+1
.endr
// 4MB Flash (Expansion bus CS0)
.rept 0x504 - 0x500
FL_SECTION_ENTRY __base,0,3,0,0,1,0
.set __base,__base+1
.endr
// Rest of Expansion bus (CS1-CS7)
.rept 0x600 - 0x510
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// 64MB Queue Manager
.rept 0x640 - 0x600
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// Unused
.rept 0xA00 - 0x640
.word 0
.set __base,__base+1
.endr
// 16MB Flash (Expansion bus CS0)
.set __base,0x500
.rept 0xA10 - 0xA00
FL_SECTION_ENTRY __base,0,3,1,0,1,0
.set __base,__base+1
.endr
// Unused
.set __base,0xA10
.rept 0xC00 - 0xA10
.word 0
.set __base,__base+1
.endr
// 1MB PCI Controller
.rept 0xC01 - 0xC00
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// 63MB Unused
.rept 0xC40 - 0xC01
.word 0
.set __base,__base+1
.endr
// 1MB Expansion bus config
.rept 0xC41 - 0xC40
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// 63MB Unused
.rept 0xC80 - 0xC41
.word 0
.set __base,__base+1
.endr
// 1MB Misc IO
.rept 0xC81 - 0xC80
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// 63MB Unused
.rept 0xCC0 - 0xC81
.word 0
.set __base,__base+1
.endr
// 1MB SDRAM Config
.rept 0xCC1 - 0xCC0
FL_SECTION_ENTRY __base,0,3,0,0,0,0
.set __base,__base+1
.endr
// 63MB Unused
.rept 0xD00 - 0xCC1
.word 0
.set __base,__base+1
.endr
// Rest is Unused
.rept 0x1000 - 0xD00
.word 0
.set __base,__base+1
.endr
I am not sure if everything is right , I modified them by referencing the grg
target , which use 32MB sdram .
3.mlt_arm_xscale_ixdp425_rom.h
#define CYGMEM_REGION_ram_SIZE (0x01000000)
#define CYGMEM_SECTION_heap1_SIZE (0x01000000 - (size_t) CYG_LABEL_NAME
(__heap1))
4.mlt_arm_xscale_ixdp425_rom.ldi
ram : ORIGIN = 0, LENGTH = 0x01000000
rom : ORIGIN = 0x50000000, LENGTH = 0x400000
5.mlt_arm_xscale_ixdp425_rom.mlt
region ram 0 01000000 0 !
Is there anything wrong ?
Thank you
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