[ECOS] problem with TIMER0 in ixp425

sumanth sumanth.kondlada@wipro.com
Wed Apr 19 08:16:00 GMT 2006


Hi,

        I am porting ecos for ixp425 for a evaluation board, i am struck up
at General purpose timer0. The pic of the ixp425 processor ,where interrupt
status register ideally should contain 0x0 but having 0x3FF040C0 , i have
checked this with cyote board which also shows the same value at restart, do
i have to do any initilizations so that interrupt status register will
become 0x0 ?. one more thing is my timestamp timer is getting updated with
its status is set and even if want to desable  timestamp timer at Timer
status register it is not clearing

but in manual of ixp425 he has given this details which was released on
october-2004
Document no: 252702-006

 
Timer Status Interrupts Get Lost During MMR Writes (SCR 1653)
Problem: An interrupt becomes lost when trying to write/clear any of the
timer status register bits (ost_sts)
from the Intel® IXP42X product line and IXC1100 control plane processors in
the same cycle that
hardware is trying to update this register when a time-out occurs.
Implication: The second timer interrupt will be lost.
20 Intel® IXP42X Product Line of Network Processors and IXC1100 Control
Plane Processor
Non-Core Errata
Workaround: Here are two possible software timer work arounds:
• Only enable one of the following timers: GP0, GP1, Timestamp, or Watchdog
interrupt. If the
watchdog timer is configured to do a soft reset, the GP0,GP1, or the
Timestamp can be used in
addition to the watchdog timer.
Note there is a counter in the IXP42X product line PMU that can be used.
• If the first work around is insufficient, an improved timer interrupt
handler would be needed.
Pseudo-code for such an improved timer handler follows:
Status: No Fix.
Does this going to effect any way

any sugessitions and poiniters are apprecited

Thanks & regards,
Sumanth.

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