[ECOS] Re: ixp425 watchdog timer

alfred hitch alfred.hitch@gmail.com
Fri Mar 18 12:34:00 GMT 2005

Thanks Mark,

I understood there were 2 issues, just that h/w guys were convinced
that the bug mentioned in errata solves flash reset issue also ..

anyways, wrote a simple script which does random read / write from
redboot   onto flash and caused watchdog reset to occur,
30 minutes of random testing showed up the bug twice .. so now they are quiet.

Thanks for your clear cut explanations here .. it really helped


On Thu, 17 Mar 2005 08:41:44 -0500, Mark Salter <msalter@redhat.com> wrote:
> On Thu, 2005-03-17 at 05:13 -0500, alfred hitch wrote:
> > hmm,
> > I had some conversation with my h/w chap and this is what we discussed :
> >
> > seems like some issue was fixed in B0 ..
> > and I was just thinking that is this possible that when there is a
> > reset signal to because of watchdog timer reset ..
> > the flash enable line is also toggled ? ? that should serve the same purpose ?
> > can anyone conform if this is the case ?? else I also dont see how
> > this thing can be solved apart from using external watchdog chip which
> > resets power to all peripherals including flash also ?
> >
> > My project lead is admant on a demo to proove that this is an issue ..
> >  (not the smartest boss here)
> >
> > Can some one tell me which mode I shall put the flash into and then
> > assert this timer to simulate this ?? I am not familiar with cfi
> > interface protocol and so if u could tell me how to recreate the
> > situation,I can temporailly screw up the cfi_cmdset0001.c to remain in
> > a specific mode only and he can have his pie -:)
> >
> There are two separate issues here. First, the errata on the watchdog
> timer reset function. That exists only in early versions of the silicon.
> The RedBoot hal has the watchdog reset commented out because the buggy
> silicon was on all of the original boards I used during development. It
> is probably okay to start using it now, but it should be configurable
> because there are still a lot boards out there populated with CPUs
> having this errata. Basically, the behavior of affected CPUs is
> unpredictable wrt watchdog timer based reset. From experience, I can
> tell you that affected systems seem to hang when the watchdog timer
> resets affected CPUs.
> The other problem is that the IXP4xx CPUs do not have a reset out line
> to indicate when a watchdog timer reset is happening. This means, that
> a reset via watchdog timer will only reset the CPU. No off-CPU devices
> will get reset. This could probably be dealt with in RedBoot, except
> that the flash won't get reset either and it may not be in read mode
> when the watchdog timer expires. If this is the case, the CPU can't
> get to the RedBoot code in flash.
> Reproducing this second problem should be easy enough. You just need to
> get the watchdog timer reset to occur while you are erasing/writing to
> flash.
> --Mark

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