[ECOS] DSRs and interrupt priority level

Enrico Piria epiria@libero.it
Thu Mar 17 13:42:00 GMT 2005

> On Wed, 2005-03-16 at 21:30 +0100, epiria@libero.it wrote:
> > Hello.
> > I have a question regarding the interrupt level at which DSRs are
> > executed.
> > I looked for an answer in previous messages to the list, but I couldn't
> > find one.
> >
> > If the architecture supports Interrupt Priority Levels, is there a
> > general policy stating at which IPL should the DSRs be executed?
> >
> > I'd say "at the lowest possible one", because DSRs have a lower priority
> > than ISRs, so, when DSRs execute, all ISRs (even those that triggered
> > the DSRs) should potentially execute again.
> > If the architecture doesn't support IPLs, "lowest priority" would still
> > mean "all interrupts enabled".
> >
> > But, I looked at some HAL implementations (for example, the
> > H8/300 and PowerPC) and it seems to me there are strange behaviours. On
> > disabled, DSRs are called at the priority level of the last interrupt.
> > Moreover, if CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING is disabled too,
> > DSRs are executed with all interrupts disabled.
> >
> > On PowerPC, there is no support for interrupt nesting. However, if
> > are not enabled before calling DSRs.
> DSRs always execute with no pending interrupts, so this really does
> not apply.  If there were any pending/current interupts, then you'd
> be executing ISR code first, even if some DSR is in progress.
> The only time that interrupt levels (nestable interrupts) matter would
> be for handling of ISRs.

I don't think this doesn't apply at all. In fact, DSRs are actually called just before the end of an interrupt handler (the HAL one, not the eCos VSR), when interrupt_end is called. So, knowing at which IPL the DSRs should be launched matters, because from this depends which ISRs can execute during DSRs execution.
However, from your answer I deduce that my assumption was correct: DSRs must execute at the lowest possible IPL, with interrupts enabled. So, before launching DSRs, the IPL (for architectures that support it) should be lowered to the minimum, and interrupts must be enabled.
This must be done:
1. Either before calling interrupt_end, or
2. during the "hal_interrupt_stack_call_pending_DSRs" routine (if the HAL defines it), before calling cyg_interrupt_call_pending_DSRs.

This still doesn't explain me the code in the HALs I mentioned in the previous mail. Why, for example, in the PowerPC HAL, interrupts are enabled just in "hal_interrupt_stack_call_pending_DSRs", present only if CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK is defined?


Enrico Piria

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