[ECOS] DSRs and interrupt priority level

epiria@libero.it epiria@libero.it
Thu Mar 17 01:49:00 GMT 2005


Hello.
I have a question regarding the interrupt level at which DSRs are
executed.
I looked for an answer in previous messages to the list, but I couldn't
find one.

If the architecture supports Interrupt Priority Levels, is there a
general policy stating at which IPL should the DSRs be executed?

I'd say "at the lowest possible one", because DSRs have a lower priority
than ISRs, so, when DSRs execute, all ISRs (even those that triggered
the DSRs) should potentially execute again.
If the architecture doesn't support IPLs, "lowest priority" would still
mean "all interrupts enabled".

But, I looked at some HAL implementations (for example, the
H8/300 and PowerPC) and it seems to me there are strange behaviours. On
the H8/300, if CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK is
disabled, DSRs are called at the priority level of the last interrupt.
Moreover, if CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING is disabled too,
DSRs are executed with all interrupts disabled.

On PowerPC, there is no support for interrupt nesting. However, if
CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK is disabled, interrupts
are not enabled before calling DSRs.

Many thanks

Enrico Piria




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