[ECOS] AT91: interrupt0 (fiq) and interrupt1 (swint) ?
Wed Sep 15 10:05:00 GMT 2004
I agree with you that maybe will be better to add some CDL entry to enable
FIQ handling in hal_IRQ_handler.
I think there is an extra cost in testing spurious interrupts too, because
in case of spurious interrupt ISR=0.
I try to do these patches and send you back.
> It means that the ISR table has 32 entries, but entries 0 and 1 are
> unused. This allows vector numbers to translate directly to table
> indexes. It simplifies the code at the expense of wasting some memory.
> So, the table slot for your FIQ handler is present. I think all you
> need to do is add a
> #define CYGNUM_HAL_INTERRUPT_FIQ 0
> somewhere and use that in your patch. It should probably go into
> var_io.h since it is generic to all AT91s and is used in generic code.
> However, in general eCos doesn't really support FIQs. The intended use
> of FIQ is for very fast, low instruction count, interrupts -- software
> DMA engines was the typical example. So the expected mechanism for
> using FIQ is for the application to replace the FIQ VSR table entry
> with a pointer to a short assembler routine. The FIQ support in the
> HAL was mainly intended to support devices where the hardware
> designers have connected a normal device to the FIQ for no good
> reason, and to be able to catch and report spurious FIQs if they
> For this reason, I think that the FIQ support in hal_IRQ_handler()
> ought to be optional, and controlled by a config option. Otherwise all
> platforms will pay the extra cost of testing for a FIQ when there is
> never any possibility of the interrupt occuring.
> Nick Garnett eCos Kernel Architect
> http://www.ecoscentric.com/ The eCos and RedBoot experts
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