[ECOS] Re: AT91 bad IRQ/FIQ priority handling?
Wed Sep 15 08:57:00 GMT 2004
"Andrea Michelotti" <email@example.com> writes:
> I think there is a bug in irq fiq priority when a FIQ and an IRQ are
> arised together. In this case IVR reading updates ISR but with the
> IRQ number not with the FIQ one. Then the irq is served instead of
> fiq (changing SMR priority doesn't change order always IRQ before
> FIQ) .
Yes, I have noticed this too. But since FIQ handling isn't really well
supported by the ARM architecture HAL, I didn't find it worthwhile to
try to make it work on the AT91 specifically.
> Is this behavior considered a bug? I did several trials with my jtst
> board a new Atmel board with an ARM7+DSP embedded (where the DSP
> generates almost simulataneous FIQs and IRQs). I did a simple patch
> that solve my problem that is a mix of old and new ecos irq handling
In our platform HAL, I solved it with a simple VSR, that triggers the
software interrupt in the AIC (see below).
The interrupt handler for the hardware device is then attached to the
SWIRQ interrupt source instead.
ldr r9,[r8,#AT91_AIC_FVR] // clear interrupt (if edge triggered)
ldr r9,=(1 << CYGNUM_HAL_INTERRUPT_SW)
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