[ECOS] ARM arch: unknown asm insn "mrc" in v5T_semantics()

Mark Salter msalter@redhat.com
Tue Mar 16 14:59:00 GMT 2004


>>>>> Heiko Panther writes:

>>> I'm targetting an ARM7 TDMI processor, and gcc 3.3.2 complains about 
>>> this inline asm instruction from function arm_stub.h:v5T_semantics().
>> 
>> 
>>> asm volatile ("mrc  p15,0,%0,c0,c0,0\n"
>>> : "=r" (id) : /* no inputs */);
>> 
>> 
>>> What's up with this insn, I can't find it in the reference. And what 
>>> should I correct to make it work?
>> 
>> 
>> Which reference? It is covered in the ARM Architectural Reference Manual.
>> The instruction reads the CPU ID register and is valid for all ARM cpus.

> My bad, I only looked in the thumb ref card. So that's an ARM 
> instruction... I'm compiling with -mthumb. I left away all the 
> thumb-interwork flags, since I don't need to integrate any ARM code 
> libs. Could that be a problem?

> Otherwise, I would probably have to switch to ARM mode before the mrc. 
> I'm gonna try that.

Or you could try the simpler approach that Daniel Neri used:

static int
v5T_semantics(void)
{
#ifdef CYGINT_HAL_ARM_ARCH_ARM7
    return 0;
#else
    unsigned id;

    asm volatile ("mrc  p15,0,%0,c0,c0,0\n"
		  : "=r" (id) : /* no inputs */);

    return ((id >> 16) & 0xff) >= 5;
#endif
}

In general, I'm pretty uncomfortable with running the stub code in thumb
mode. For most ARM CPUs, the cache flushes done in the stub use co-proc
insns not available in thumb mode. There are also those CPUs with h/w
breakpoint/watchpoint support which require the stub to use non-thumb
insns to manipulate.

--Mark




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