[ECOS] MIPS interrupts

[Sebastian Uchman]

Hello all,

I got few questions about MIPS32 4Kc on Malta Board:
I would like to use Real Time Clock to generate interrupts. 
I set the compare register on a value (0x0000ffff). Then the count register 
become the value 0x0000ffff (while it runs), and the cause register shows 
0x00008000 and the status 0x1000ff03. But it does nothing. It should go to my 
ISR but nothing happens. 
What does MIPS do when an interrupt occurs? 
Where does it go first?
Where should be placed my ISR? 
Are there any other register ,which should be set or unset?

greetings

sebastian uchman


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