[ECOS] HAL_INTERRUPT_ACKNOWLEDGE on mips

[Andy Dyer]

looking in hal/mips/arch/current/include/hal_intr.h
I see the generic implementation of HAL_INTERRUPT_ACKNOWLEDGE
for mips tries to write back into the Cause register
(CP0 register $13), presumably to clear the IP[7:2]
bits.

All of the books I have handy say that the only fields
in that register that are writable are IP[1:0]
(sometimes used to allow s/w to generate interrupts)
and those aren't touched by this code.

Is there some variant where this isn't true or can this
code be removed?

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Andrew Dyer               |  adyer@righthandtech.com
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