[ECOS] context for creating interrupts on edb7312

[Aaron Case]

> It happens automatically in "cyg_start()", so my test runs just as well
> even if I make this change:
>
> Index: hal/powerpc/mpc8xxx/current/tests/mpc8xxx_timer.c
> ===================================================================
> RCS file:
> /home/gthomas/my_cvs/develop/ecos/packages/hal/powerpc/mpc8xxx/cur
> rent/tests/mpc8xxx_timer.c,v
> retrieving revision 1.1
> diff -u -5 -p -r1.1 mpc8xxx_timer.c
> --- hal/powerpc/mpc8xxx/current/tests/mpc8xxx_timer.c   20 Nov 2003
> 14:21:54 -0000      1.1
> +++ hal/powerpc/mpc8xxx/current/tests/mpc8xxx_timer.c   20 Nov 2003
> 14:29:39 -0000
> @@ -149,12 +149,12 @@ cyg_user_start( void )
>      IMM->cpm_timers_trr1 = 0x2000;  // Reference value
>      IMM->cpm_timers_tcn1 = 0;
>      IMM->cpm_timers_ter[0] = 0xFF;
>      IMM->cpm_timers_tgcr1 = _TC_TGCR_RST1;  // Reset & enable timer1
>
> -    cyg_scheduler_start();
> -    CYG_TEST_PASS("mpc8xxx_timer");
> +//    cyg_scheduler_start();
> +//    CYG_TEST_PASS("mpc8xxx_timer");
>  }
>
>  //
> -------------------------------------------------------------------------
>
>  #else  // ! CYGPKG_KERNEL
>
> Are you overriding "cyg_start()"?  That's the place that the scheduler
> is normally started (although many of our tests do it explicitly)
>
> --
> Gary Thomas <gary@mlbassoc.com>
> MLB Associates
>
>

Thanks for the clarification. I believe this may be my last question on the
matter.

Is it possible to enable interrupts with cyg_interrupt_enable(), before the
task scheduler starts, supposing I were foolish enough to do such a thing?

It appears that cyg_interrupt_enable() acts directly on the CPSR in
ARM(after viewing the ASM), but my MAJIC debugger tells me that the CPSR
doesn't change unless the scheduler is started. So what in eCos blocks
access to the interrupt bits in the CPSR when the scheduler is not running?


Thanks,
Aaron Case



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