[ECOS] S3C4510: invalidate cache

Roland Caßebohm roland.cassebohm@visionsystems.de
Wed Nov 5 09:24:00 GMT 2003


On Dienstag, 4. November 2003 17:31, Jay Foster wrote:
> Yes, make sure that the value for KS32C_CACHE_SETx_ADDR are correct for
> your processor.  These are defined in plf_io.h.
>
> //-------------------------------------------------------------------------
>- ---
> // Cache
> #if defined(CYG_HAL_CPUTYPE_KS32C5000A)	// Now known as the S3C4500
> #define KS32C_CACHE_SET0_ADDR       0x14000000
> #define KS32C_CACHE_SET1_ADDR       0x14800000
> #define KS32C_CACHE_TAG_ADDR        0x15000000
> #else  // S3C4510[AB]=KS32C50100[AB], S3C4530=KS32C50300
> #define KS32C_CACHE_SET0_ADDR       0x10000000
> #define KS32C_CACHE_SET1_ADDR       0x10800000
> #define KS32C_CACHE_TAG_ADDR        0x11000000
> #endif
>
> Yes, the only difference between these two is the non-cachable address bit.
> The User Manual for the S3C4510B indicates the addresses to use.  The cache
> tag line address space is not part of the cachable/non-cachable address
> space.  I didn't have access to the manual for the S3C4500, so I just
> defined the correct values for the S3C4510B and left the existing code
> unchanged.  You may be right in that the values are wrong for all variants.
>

I have just looked in older snds code from Grant Edwards, there has been used
0x11000000 for both variants. But I have also only the manual of the S3C4510,
so I don't know about S3C4500.

Best regards,
Roland

-- 
Before posting, please read the FAQ: http://sources.redhat.com/fom/ecos
and search the list archive: http://sources.redhat.com/ml/ecos-discuss



More information about the Ecos-discuss mailing list