[ECOS] Attributes to local varables of class

Nick Garnett nickg@ecoscentric.com
Wed May 14 17:06:00 GMT 2003


Brij Bihari Pandey <fuzzhead012@yahoo.com> writes:

> hi Nick,
> 
> > I added these annotations some time ago to support a platform that
> > had a very steep timing difference between a very small CPU-local RAM
> > area and the main part of RAM. The idea was to move some critical
> > static data into the local RAM for better performance.
> which of the architecture under packages/hal/ it is? 
> 
> > It looks like you have found a place where I was being a little too
> > enthusiatic with adding the annotations. They are indeed not necessary
> > on dsr_count and next_dsr. However, the annotations have no effect in
> > this case.
> may be unintended things can be removed from the code, to avoid unnecessary
> confusions.
> 
> While looking at the same code, another doubt popped off in my head.
> dsr_list is a static array of size NumCPUs and the variables dsr_list and
> dsr_count are local to the Cyg_Interrupt class.
> Now this could mean that two different objects might have two different values
> for these local variables and both might be accessing/modifying/updating the
> same dsr_list?
> Quite confusing! Has it been a problem some user so far might have pointed it
> out, but no one seems to have. That means somehow things are working right!
> To answer this confusion, I navigated the sources and found - 
> eCos is creating only NumCPUs objects of type Cyg_Interrupt in the form of
> cyg_sched_cpu_interrupt array in sched.cxx. Are these the only instances of
> Cyg_Interrupt class?
> What if some user adds one more of Cyg_Interrupt object? manipulation of
> dsr_list via dsr_count and next_dsr can go for a toss??
> 
> If the answer out of above confusion is -- never should there be more than
> NumCPUs instances of class Cyg_Interrupt -- then why do we need to make
> dsr_list as an array and that too as static?
> 

There can be any number of interrupt objects. When an ISR posts a DSR,
the interrupt object is placed on the DSR list for the current CPU. We
currently only support assignment of interrupts to specific CPUs, we
don't support dynamic allocation. Access to each DSR list is
serialized by simply disabling interrupts on that CPU, since CPUs
don't access other CPU's DSR lists.

-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com/     The eCos and RedBoot experts


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