[ECOS] Vr4131 porting issues

Jonathan Larmour jifl@eCosCentric.com
Tue Mar 25 11:11:00 GMT 2003


Nick Garnett wrote:
> "Jurica Baricevic" <jura@INTESIS.hr> writes:
>>Just to clarify some 64/32-bit things. If I noticed well - the Vr4300
>>eCos is by default switching CPU in 64-bit access mode (bit KX in
>>status register), but the C code is built with -mpg32 to avoid usage of
>>64-bit instructions. Some assembler routines use ld/sd though. Am I right?
> 
> 
> Yes. eCos and RedBoot continue to run in 32 bit mode, but we context
> switch the whole 64 bit machine state. This was originally as a result of
> some bugs in the toolchain: the -mgp32 wasn't being passed on to the
> assembler, so it still thought it was building for 64 bits and
> generated some 64 bit instructions. 

Actually it wasn't a bug after all. It was a "feature" ;-). If we had 
wanted to do true MIPS 2 ISA, then we would have had 32-bit GPRs *and* 
FPRs, and we would lose half the register set (because of the way that FPR 
register splitting/renumbering stuff works when doing MIPS2 on a MIPS3 
CPU). So to keep all the FPRs, we used -mgp32, or including the implicit 
values, -mips3 -mgp32 -mfp64.

However when manipulating 64-bit FPRs to/from memory, there was a 
particular situation where you couldn't load 64-bit FPRs except using 
32-bit GPRs, so temporarily GCC puts the 64-bit value into the GPR. I 
can't remember why, but MFC1/MTC1 couldn't be used for some reason - 
Andrew Haley knew why.

Some ports, like the tx49, decided to ignore all this hassle[1] and just 
use -mips2. Given all the problems we had with getting -mgp32 working, 
particularly with floating point, I think it's the safer route, at the 
expense of losing half the FP register set and adding extra instruction 
overhead when loading/storing FPRs.

Jurica - you should look and see what the libm tests do. I fancy the 
chances they'll barf badly.

Jifl
[1] Well, actually, tx49 started down this route, but it proved too 
difficult getting the tools working iwth -mgp32.
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