[ECOS] Vr4131 porting issues

[Bart Veer]

>>>>> "Jura" == Jurica Baricevic <jura@INTESIS.hr> writes:

    >> > I have a dumb question: what should MIPS ISA 32 stand for? I
    >> > am acquainted with the ISA 1/2/3 - but don't get what should
    >> > ISA 32 exactly represent.
    >> 
    >> Not such a dumb question, I have trouble keeping track of which
    >> MIPS ISA is which, particularly when the device numbering bears
    >> no relationship to it at all :-)
    >> 
    >> MIPS32 and MIPS64 are newer versions of the ISA specification,
    >> aimed mainly at embedded use. They are essentially MIPS 3 with
    >> a little MIPS 4 mixed in. Most recent MIPS implementations,
    >> like the NEC VR4XXX series and the Toshiba TX49, while not
    >> explicitly MIPS32/64 compliant, are at least supersets of these
    >> specifications. So the MIPS32/64 toolchain will generate code
    >> that will run on them.

    Jura> Sounds great. Bart seems much more reserved with this issue
    Jura> though. He made me think that the mips64vr4100-elf would be
    Jura> the only safe path to go.

I am not sure I meant to imply that.

The problem is that the mipsisa32-elf toolchain may never have been
tested on the NEC VR4xxx series, or on a TX49. Ideally you would not
use a toolchain for a given processor unless it has been tested,
possibly just a full run of eCos tests, preferably a full run of the
gcc testsuite as well. The toolchain should work, but unpleasant
surprises are possible.

On the other hand it is also possible that nobody has built, let alone
tested, a mips64vr4xxx-elf toolchain using gcc 3.2.1 sources. If so
then there would be no reason to prefer a mips64vr4xxx toolchain
to a mipsisa32 toolchain. Either toolchain could be broken in various
subtle or unsubtle ways. There may be information in the gcc mailing
lists or on their web site about which targets have been tested.

Bart

-- 
Bart Veer                       eCos Configuration Architect
http://www.ecoscentric.com/     The eCos and RedBoot experts

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